Re: [PATCH 1/2] MIPS: Allow MIPS32R2 kernel to run on P5600 and M5150

From: Jiaxun Yang
Date: Tue May 30 2023 - 06:12:21 EST

> 2023年5月30日 09:03,Maciej W. Rozycki <macro@xxxxxxxxxxx> 写道:
> On Mon, 29 May 2023, Jiaxun Yang wrote:
>> M5150 and P5600 are two MIPS32R5 kernels, however as MIPS32R5 is
>> backward compatible with MIPS32R2 there is no reason to forbid
>> M5150 and P5600 on MIPS32R2 kernel.
> What problem are you trying to solve? The CONFIG_SYS_HAS_CPU_* settings
> denote overall platform's support for the given CPU and have nothing to do
> with what architecture level a given kernel has been configured for. You
> do need to get the settings right for your platform, just as you do in
> 2/2, but this 1/2 part looks wrong to me.

Well the universal target is to allow R2 generic kernel to run on R5 CPUs.
As R5 is backward compatible we can just have one universal kernel binary.

Allowing P5600 and M5150 to run on R2 kernel does not bring much overhead.
In fact only several bytes are added to kernel binary.

(Actually although M5150 is advertising as R5 it’s technically R2 because it does
not implement some features mandatory for R5.)

- Jiaxun

> NB CPU_4KEC is double-listed as R1 and R2 because early revisions of the
> 4KEc core were actually R1 before switching to R2, so this CPU can report
> either revision.
> I don't know why CPU_XBURST is also listed as both R1 and R2, the history
> looks convoluted with no explanation. Paul, is the CPU also dual-revision
> or is it just a bug and it is supposed to be listed under one ISA revision
> only, presumably R2?
> Maciej