Re: [PATCH v2 12/12] dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string

From: Frank Li
Date: Tue May 30 2023 - 09:57:41 EST


On Tue, May 30, 2023 at 03:08:48PM +0200, Krzysztof Kozlowski wrote:
> > diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> > index 5fd8fc604261..eed12687b0c9 100644
> > --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> > +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> > @@ -21,6 +21,10 @@ properties:
> > - enum:
> > - fsl,vf610-edma
> > - fsl,imx7ulp-edma
> > + - fsl,imx8qm-edma
> > + - fsl,imx8qm-adma
> > + - fsl,imx93-edma3
> > + - fsl,imx93-edma4
>
> What are these last two? What is "3" and "4"?

imx93 edma have two version, edma3(AHB) and edma4(AXI).
There are little bit difference at channel space size.

+static struct fsl_edma_drvdata imx93_data3 = {
+ .version = v3,
+ .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK,
+ .chreg_space_sz = 0x10000,
+ .chreg_off = 0x10000,
+ .setup_irq = fsl_edma3_irq_init,
+};
+
+static struct fsl_edma_drvdata imx93_data4 = {
+ .version = v4,
+ .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK,
+ .chreg_space_sz = 0x8000,
+ .chreg_off = 0x10000,
+ .setup_irq = fsl_edma3_irq_init,
+};

>
> > - items:
> > - const: fsl,ls1028a-edma
> > - const: fsl,vf610-edma
> > @@ -101,6 +105,22 @@ allOf:
> > reg:
> > maxItems: 2
> >
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + anyOf:
> > + - const: fsl,imx8qm-edma
> > + - const: fsl,imx8qm-adma
> > + - const: fsl,imx93-edma3
> > + - const: fsl,imx93-edma4
> > + then:
> > + properties:
> > + reg:
> > + maxItems: 1
> > + interrupts:
> > + maxItems: 64
>
> That's odd. What about the names? What about minItems? Anyway, this
> wasn't tested - you will have failures with dtbs_check.

It passed dtbs_check. interrupt-names is optional property, which
will no used after edma v3.

Planned dts look like:

+ edma1: dma-controller@44000000{
+ compatible = "fsl,imx93-edma3";
+ reg = <0x44000000 0x200000>;
+ #dma-cells = <3>;
+ dma-channels = <31>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
....
+ };



>
>
>
> Best regards,
> Krzysztof
>