Re: [PATCH v2] mmc: mtk-sd: reduce CIT for better performance

From: AngeloGioacchino Del Regno
Date: Wed May 31 2023 - 04:18:51 EST

Il 31/05/23 09:32, Wenbin Mei (梅文彬) ha scritto:
On Thu, 2023-05-18 at 11:13 +0200, AngeloGioacchino Del Regno wrote:
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Il 10/05/23 03:58, Wenbin Mei ha scritto:
CQHCI_SSC1 indicates to CQE the polling period to use when using
The default value 0x1000 that corresponds to 150us, let's decrease
it to

The default value 0x1000 (4096) corresponds to 4096 * 52.08uS =
231.33uS the default is not 150uS.

If I'm wrong, this means that the CQCAP field is not 0, which would
that the expected 3uS would be wrong.

Also, since the calculation can be done dynamically, this is what we
actually do in the driver, as this gives information to the next
checking this piece of code.

Apart from this, by just writing 0x40 to the CQHCI_SSC1 register, you
assuming that the CQCAP value requirement is fullfilled, but you
assume that the bootloader has set the CQCAP's ITCFVAL and ITCFMUL
as you expect on all platforms: this means that implementing this
a little more effort.

You have two ways to implement this:
*** First ***
1. Read ITCFMUL and ITCFVAL, then:
tclk_mul = itcfmul_to_mhz(ITCFMUL); /* pseudo function
interprets reg value*/
tclk = ITCFVAL * tclk_mul;

2. Set SSC1 so that we get 3nS:
#define CQHCI_SSC1_CIT GENMASK(15, 0)
poll_time = cit_time_ns_to_regval(3);
sscit = FIELD_PREP(CQHCI_SSC1_CIT, poll_time)
cqhci_writel( ... )

*** Second **

1. Pre-set ITCFMUL and ITCFVAL to
ITCFVAL = 192 (decimal)
ITCFMUL = 2 (where 2 == 0.1MHz)

2. Set SSC1 so that we get 3nS:
#define CQHCI_SSC1_CIT GENMASK(15, 0)
poll_time = cit_time_ns_to_regval(3);
sscit = FIELD_PREP(CQHCI_SSC1_CIT, poll_time)
cqhci_writel( ... )

I would implement the first way, as it paves the way to extend this
to different
tclk values if needed in the future.

Hi Angelo,

Sorry for lately reply.

For Mediatek mmc host IP, ITCFMUL is 0x2(0x1MHz), ITVFVAL reports 182,
and these fields are the same and are readonly for all IC, but since
Mediatek CQE uses msdc_hclk(273MHz), CMD13'interval calculation driver
should use 273MHz to get the actual time, so the actual clock is

You're right, I've misread the datasheet, just rechecked and it reports RO.

If CIT is 0x1000 by default, CMD idle time: 0x1000 * 1 / 27.3MHz =
around 150us.

In addition the bootloader will not set the CQCAP's ITCFVAL and ITCFMUL
fields, because these fields of CQCAP register is RO(readonly), so we
can ignore the change for the CQCAP's ITCFVAL and ITCFMUL fields.

Yes, that's right, again - this means that you should go for the first
proposed implementation, as future MediaTek SoCs may (or may not) change
that: if you implement as proposed, this is going to be a one-time thing
and future SoCs won't need specific changes.

That implementation also documents the flow about how we're getting to
the actual value, which is important for community people reading this
driver in the future for debugging purposes.



0x40 that corresponds to 3us, which can improve the performance of
eMMC devices.

Signed-off-by: Wenbin Mei <wenbin.mei@xxxxxxxxxxxx>
drivers/mmc/host/mtk-sd.c | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index edade0e54a0c..ffeccddcd028 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -2453,6 +2453,7 @@ static void msdc_hs400_enhanced_strobe(struct
mmc_host *mmc,
static void msdc_cqe_enable(struct mmc_host *mmc)
struct msdc_host *host = mmc_priv(mmc);
+ struct cqhci_host *cq_host = mmc->cqe_private;

/* enable cmdq irq */
writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
@@ -2462,6 +2463,9 @@ static void msdc_cqe_enable(struct mmc_host
msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
/* default read data timeout 1s */
msdc_set_timeout(host, 1000000000ULL, 0);
+ /* decrease the send status command idle timer to 3us */
+ cqhci_writel(cq_host, 0x40, CQHCI_SSC1);

static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)