Re: [PATCH v6 5/6] drm/etnaviv: add driver support for the PCI devices

[Sui Jingfeng]

Hi,

On 2023/6/1 00:23, Lucas Stach wrote:
> Hi Sui Jingfeng,
>
> Am Donnerstag, dem 01.06.2023 um 00:08 +0800 schrieb Sui Jingfeng:
> > Hi,
> >
> > On 2023/5/31 03:02, Bjorn Helgaas wrote:
> > > On Wed, May 31, 2023 at 12:06:42AM +0800, Sui Jingfeng wrote:
> > > > This patch adds PCI driver support on top of what already have. Take the
> > > > GC1000 in LS7A1000/LS2K1000 as the first instance of the PCI device driver.
> > > > There is only one GPU core for the GC1000 in the LS7A1000 and LS2K1000.
> > > > Therefore, component frameworks can be avoided. Because we want to bind the
> > > > DRM driver service to the PCI driver manually.
> > > > +	 * Loongson Mips and LoongArch CPU(ls3a5000, ls3a4000, ls2k1000la)
> > > > +	 * maintain cache coherency by hardware
> > > > +	 */
> > > > +	if (IS_ENABLED(CONFIG_CPU_LOONGSON64) || IS_ENABLED(CONFIG_LOONGARCH))
> > > > +		priv->has_cached_coherent = true;
> > > This looks like something that should be a runtime check, not a
> > > compile-time check.
> > >
> > > If it's possible to build a single kernel image that runs on Loongson
> > > MIPS or LoongArch CPU and, in addition, runs on other platforms, you
> > > cannot assume that all the others maintain this cache coherency.
> > Nice catch! I don't even realize this!
> >
> >
> > LS3A4000 is mips64r2 with MSA SIMD, while LS3A5000 is LoongArch,
> >
> > instruction set, compiler, and binary interface are totally changed.
> >
> > Therefore, it's impossible to build a single kernel image that runs on
> > all Loongson CPUs.
> >
> > Currently, I can guarantee that this works on the Loongson platform.
> >
> > My initial intent here is to let priv->has_cached_coherent be *true* on
> > the Loongson platform (both mips and loongarch).
> >
> > I do know there are some other vendors who bought GPU IP from Vivante.
> >
> > say GC7000, and integrate it into their discrete GPU product.
> >
> > But it is also a PCI device, but this is another story; it deserves
> > another patch.
> >
> > I don't know if Etnaviv folk find some similar hardware on Arm Arch,
> >
> > Some Arm CPUs do not maintain cached coherency on hardware.
> >
> > The has_cached_coherent member can be set to false on such hardware.
> >
> > For us, it seems that there is no need to do runtime checking,
> >
> > because they are all cached coherent by default.
> >
> >
> > Can I improve this in the future, currently I don't have a good idea.
> I think I mentioned before that this needs to be a runtime check. What
> does dev_is_dma_coherent() return for the Vivante GPU device on your
> platform?

I have tested, it return *true*.

Yeah, out hardware is dma coherent.

Then,  we switching  to  dev_is_dma_coherent(dev) ?

> Regards,
> Lucas

--
Jingfeng