On Mon, 5 Jun 2023 at 14:30, Suzuki K Poulose <suzuki.poulose@xxxxxxx> wrote:
Instead of adding the PIDs forever to the list for the new CPUs, let us detect
a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and
DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID
matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always.
Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@xxxxxxx
Cc: Anshuman Khandual <anshuman.khandual@xxxxxxx>
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: frowand.list@xxxxxxxxx
Cc: linux@xxxxxxxxxxxxxxx
Cc: Mike Leach <mike.leach@xxxxxxxxxx>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
+#define PIDR2_JEDEC BIT(3)Reviewed by:- Mike Leach <mike.leach@xxxxxxxxxx>
+#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
+/*
+ * Match all PIDs in a given CoreSight device type and architecture, defined
+ * by the uci.
+ */
+#define CS_AMBA_MATCH_ALL_UCI(uci) \
+ __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
/* extract the data value from a UCI structure given amba_id pointer. */
static inline void *coresight_get_uci_data(const struct amba_id *id)
--
2.34.1