On Thu, May 11, 2023, Yang Weijiang wrote:
The last patch is introduced to support supervisor SHSTK but the feature isI am beyond confused by the SDM's wording of CET_SSS.
not enabled on Intel platform for now, the main purpose of this patch is to
facilitate AMD folks to enable the feature.
First, it says that CET_SSS says the CPU isn't buggy (or maybe "less buggy" is
more appropriate phrasing).
Bit 18: CET_SSS. If 1, indicates that an operating system can enable supervisor
shadow stacks as long as it ensures that certain supervisor shadow-stack pushes
will not cause page faults (see Section 17.2.3 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1).
But then it says says VMMs shouldn't set the bit.
When emulating the CPUID instruction, a virtual-machine monitor should return
this bit as 0 if those pushes can cause VM exits.
Based on the Xen code (which is sadly a far better source of information than the
SDM), I *think* that what the SDM is trying to say is that VMMs should not set
CET_SS if VM-Exits can occur ***and*** the bit is not set in the host CPU. Because
if the SDM really means "VMMs should never set the bit", then what on earth is the
point of the bit.
In summary, this new series enables CET user SHSTK/IBT and kernel IBT, butWhy? If my interpretation of the SDM is correct, then all the pieces are there.
doesn't fully support CET supervisor SHSTK, the enabling work is left for
the future.
[...]