Re: A question about prefetchw detection in "x86/asm: Cleanup prefetch primitives"

[Xi Ruoyao]

On Wed, 2023-06-21 at 19:18 +0800, Xi Ruoyao wrote:
> On Wed, 2023-06-21 at 13:13 +0200, Borislav Petkov wrote:
> > On Wed, Jun 21, 2023 at 06:57:40PM +0800, Xi Ruoyao wrote:
> > > I intend to implement the same logic for Glibc.  I can understand "3DNow
> > > implies PREFETCHW", but is there a bibliographical reference about "LM
> > > implies PREFETCHW" so I can convince the Glibc maintainers for the
> > > change?
> > 
> > https://www.amd.com/system/files/TechDocs/24594.pdf
> 
> Thanks very much!

Hmm, while it's true for AMD, the Intel SDM claims otherwise.  It says
prefetchw is only (really) supported with "Intel® Core™ M processor
family; 5th Generation Intel® Core™ processor family, Intel Atom
processor based on Silvermont microarchitecture" or later.  On the
earlier Intel CPUs supporting LM, the prefetchw instruction is treated
as NOP.

Is the kernel code an oversight or we simply don't want to bother
checking Intel vs. AMD here?

-- 
Xi Ruoyao <xry111@xxxxxxxxxxx>
School of Aerospace Science and Technology, Xidian University