Re: [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors

[Terry Bowman]

Hi Jonathan,

Thanks for the reviews.

On 6/22/23 08:16, Jonathan Cameron wrote:
> On Wed, 21 Jun 2023 22:51:22 -0500
> Terry Bowman <terry.bowman@xxxxxxx> wrote:
> 
>> The restricted CXL host (RCH) error handler will log protocol errors
>> using AER and RAS status registers. The AER and RAS registers need
>> to be virtually memory mapped before enabling interrupts. Update
>> __devm_cxl_add_dport() to include RCH RAS and AER mapping.
>>
>> Add 'struct cxl_regs' to 'struct cxl_dport' for saving a unique copy of
>> the RCH downstream port's mapped registers.
> 
> Copy of the address at which they are mapped, not the registers.
> Probably worth tweaking description to make that clearer.
> 

Good point. I'll change to the following:

"Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
the RCH downstream port's AER and RAS registers."

Regards,
Terry