Re: [PATCH V3] perf vendor events riscv: add T-HEAD C9xx JSON file

[Namhyung Kim]

Hello,

On Sat, Jun 24, 2023 at 1:54 AM Conor Dooley <conor@xxxxxxxxxx> wrote:
>
> On Fri, Jun 23, 2023 at 09:35:01PM -0700, Namhyung Kim wrote:
> > On Fri, Jun 23, 2023 at 6:33 PM Inochi Amaoto <inochiama@xxxxxxxxxxx> wrote:
>
> > >
> > > As for c9xx wildcard, the T-HEAD provides a `MCPUID` vendor CSR to allow
> > > its CKLINK to get the detail CPU info. The format of this CSR are:
> > >
> > > ------------------------------------------------
> > > |31   28|27  26|25    22|21   18|17    8|7    0|
> > > | index | WLRL | family | class | model | WLRL |
> > > ------------------------------------------------
> > >
> > > And for C9xx series (only index 0000 is vaild for us, as `MCPUID` also
> > > provides other index).
> > >
> > > | 0000 | xx | 0100 | class | xxxxxxxxxx | xxxxxxxx |
> > >
> > > The class codes are:
> > >
> > > C910: 0011
> > > c906: 0100
> > >
> > > The CSR is a M-mode only CSR, so now I'm exploring a clean way to
> > > integrate this CSR into the kernel. Any advice?
>
> See for example how riscv_cpuinfo_starting() reads mvendorid & Co.
>
> > I don't know about the details.  Is this CSR available from user space?
> > If not, you could add it somewhere in the sysfs.
>
> Machine mode is the highest privilege level, Supervisor mode is next &
> User mode is the lowest. Typically the kernel runs in Supervisor mode.

Maybe you're interested in this thread for user visible identifiers.

https://lore.kernel.org/all/1687245156-61215-1-git-send-email-renyu.zj@xxxxxxxxxxxxxxxxx/

Thanks,
Namhyung