[PATCH] PCI: j721e: Fix delay before PERST# deassert

[Achal Verma]

As per the PCIe Card Electromechanical specification REV. 3.0, PERST#
signal should be de-asserted after minimum 100ms from the time power-rails
become stable. Current delay of 100us is observed to be not enough on some
custom platform implemented using TI's K3 SOCs.

So, to ensure 100ms delay to give sufficient time for power-rails and
refclk to become stable, change delay from 100us to 100ms.

>From PCIe Card Electromechanical specification REV. 3.0 section 2.6.2:
TPVPERL: Power stable to PERST# inactive - 100ms
T-PERST-CLK: REFCLK stable before PERST# inactive - 100 usec.

Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver")
Signed-off-by: Achal Verma <a-verma1@xxxxxx>
---
 drivers/pci/controller/cadence/pci-j721e.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index e70213c9060a..fa2b4c11d2c4 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -499,13 +499,12 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 		/*
 		 * "Power Sequencing and Reset Signal Timings" table in
 		 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
-		 * indicates PERST# should be deasserted after minimum of 100us
-		 * once REFCLK is stable. The REFCLK to the connector in RC
-		 * mode is selected while enabling the PHY. So deassert PERST#
-		 * after 100 us.
+		 * indicates PERST# should be deasserted after minimum of 100ms
+		 * after power rails achieve specified operating limits and
+		 * within this period reference clock should also become stable.
 		 */
 		if (gpiod) {
-			usleep_range(100, 200);
+			msleep(100);
 			gpiod_set_value_cansleep(gpiod, 1);
 		}
 
-- 
2.25.1