Re: [PATCH 4/6] arm64: dts: qcom: ipq5332: Add tsens node

[Praveenkumar I]

On 7/10/2023 4:51 PM, Dmitry Baryshkov wrote:
> On 10/07/2023 13:37, Praveenkumar I wrote:
> > IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsense
> > node with nvmem cells for calibration data.
> >
> > Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/ipq5332.dtsi | 113 ++++++++++++++++++++++++++
> >   1 file changed, 113 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi 
> > b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> > index 8bfc2db44624..a1e3527178c0 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> > @@ -150,6 +150,91 @@ qfprom: efuse@a4000 {
> >               reg = <0x000a4000 0x721>;
> >               #address-cells = <1>;
> >               #size-cells = <1>;
> > +
> > +            tsens_mode: mode@3e1 {
> > +                reg = <0x3e1 0x1>;
> > +                bits = <0 3>;
> > +            };
> > +
> > +            tsens_base0: base0@3e1 {
> > +                reg = <0x3e1 0x2>;
> > +                bits = <3 10>;
> > +            };
> > +
> > +            tsens_base1: base1@3e2 {
> > +                reg = <0x3e2 0x2>;
> > +                bits = <5 10>;
> > +            };
> > +
> > +            s0_offset: s0_offset@3e4 {
> > +                reg = <0x3e4 0x1>;
> > +                bits = <0 4>;
> > +            };
> > +
> > +            s3_offset: s3_offset@3e5 {
> > +                reg = <0x3e5 0x1>;
> > +                bits = <4 4>;
> > +            };
> > +
> > +            s4_offset: s4_offset@3e6 {
> > +                reg = <0x3e6 0x1>;
> > +                bits = <0 4>;
> > +            };
> > +
> > +            s5_offset: s5_offset@3e6 {
> > +                reg = <0x3e6 0x1>;
> > +                bits = <4 4>;
> > +            };
> > +
> > +            s6_offset: s6_offset@3e8 {
> > +                reg = <0x3e8 0x1>;
> > +                bits = <0 4>;
> > +            };
> > +
> > +            s7_offset: s7_offset@3e8 {
> > +                reg = <0x3e8 0x1>;
> > +                bits = <4 4>;
> > +            };
> > +
> > +            s8_offset: s8_offset@3a4 {
> > +                reg = <0x3a4 0x1>;
> > +                bits = <0 4>;
> > +            };
> > +
> > +            s9_offset: s9_offset@3a4 {
> > +                reg = <0x3a4 0x1>;
> > +                bits = <4 4>;
> > +            };
> > +
> > +            s10_offset: s10_offset@3a5 {
> > +                reg = <0x3a5 0x1>;
> > +                bits = <0 4>;
> > +            };
> > +
> > +            s11_offset: s11_offset@3a5 {
> > +                reg = <0x3a5 0x1>;
> > +                bits = <4 4>;
> > +            };
> > +
> > +            s12_offset: s12_offset@3a6 {
> > +                reg = <0x3a6 0x1>;
> > +                bits = <0 4>;
> > +            };
> > +
> > +            s13_offset: s13_offset@3a6 {
> > +                reg = <0x3a6 0x1>;
> > +                bits = <4 4>;
> > +            };
> > +
> > +            s14_offset: s14_offset@3ad {
> > +                reg = <0x3ad 0x2>;
> > +                bits = <7 4>;
> > +            };
> > +
> > +            s15_offset: s0_offset@3ae {
> > +                reg = <0x3ae 0x1>;
> > +                bits = <3 4>;
> > +            };
> >           };
> >             rng: rng@e3000 {
> > @@ -159,6 +244,34 @@ rng: rng@e3000 {
> >               clock-names = "core";
> >           };
> >   +        tsens: thermal-sensor@4a9000 {
> > +            compatible = "qcom,ipq5332-tsens";
> > +            reg = <0x4a9000 0x1000>,
> > +                  <0x4a8000 0x1000>;
> > +            nvmem-cells = <&tsens_mode>, <&tsens_base0>,
> > +                    <&tsens_base1>, <&s0_offset>,
>
> Please align vertically.
Sure, will change in next patch.
> > + <&s3_offset>, <&s4_offset>,
> > +                    <&s5_offset>, <&s6_offset>,
> > +                    <&s7_offset>, <&s8_offset>,
> > +                    <&s9_offset>, <&s10_offset>,
> > +                    <&s11_offset>, <&s12_offset>,
> > +                    <&s13_offset>, <&s14_offset>,
> > +                    <&s15_offset>;
> > +            nvmem-cell-names = "mode", "base0",
> > +                        "base1", "s0_offset",
>
> And here.
Sure, will change in next patch.
> > +                        "s3_offset", "s4_offset",
> > +                        "s5_offset", "s6_offset",
> > +                        "s7_offset", "s8_offset",
> > +                        "s9_offset", "s10_offset",
> > +                        "s11_offset", "s12_offset",
> > +                        "s13_offset", "s14_offset",
> > +                        "s15_offset";
> > +            interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
> > +            interrupt-names = "combined";
> > +            #qcom,sensors = <16>;
> > +            #thermal-sensor-cells = <1>;
> > +        };
> > +
> >           tlmm: pinctrl@1000000 {
> >               compatible = "qcom,ipq5332-tlmm";
> >               reg = <0x01000000 0x300000>;