Re: [PATCH 2/2] clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes

[Alexandre Mergnat]

On 17/07/2023 16:30, AngeloGioacchino Del Regno wrote:
> > > > > However I'm not sure if that works for parents. It should, given the
> > > > > original use case was for the sunxi platforms, which like the MediaTek
> > > > > platform here has 2 PLLs for video related consumers, but I couldn't
> > > > > find code verifying it.
> > > >
> > > > If you want to prevent clocks from ever being reparented, you can use
> > > > the new clk_hw_determine_rate_no_reparent() determine_rate
> > > > implementation.
> > >
> > > We want the clocks to be reparented, as we need them to switch 
> > > parents as
> > > explained before... that's more or less how the tree looks:
> > >
> > > TVDPLL(x) -> PLL Divider (fixed) -> MUX -> Gate -> Controller
> > >
> > > Besides, I think that forcing *one* parent to the dp/edp mux would 
> > > produce a
> > > loss of the flexibility that the clock framework provides.
> > >
> > > I again want to emphasize on the fact that TVDPLL1 and TVDPLL2 are 
> > > *identical*
> > > in specs, and on that there will never be a MT8195 SoC that has only 
> > > one of
> > > the two PLLs, for obvious reasons...
> > >
> > > P.S.: If you need more context, I'll be glad to answer to any other 
> > > question!
> >
> > Then I have no idea what the question is :)
> >
> > What are you trying to achieve / fix, and how can I help you ? :)
>
> Chen-Yu, Alexandre had/have questions about if there was any other 
> solution instead
> of using the solution of *this* commit, so, if there's any other better 
> solution
> than the one that I've sent as this commit.
>
> I'm the one saying that this commit is the best solution :-P

Hi Angelo,

My solution is based on PLL static allocation, because I missed it could 
be reparented actually. I think I've a better understanding of this 
commit now, thanks to your explanations. Looks fine for me.

Reviewed-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>

--
Regards,
Alexandre