Re: [PATCH] LoongArch: Fixup cmpxchg sematic for memory barrier

[WANG Rui]

Hello,

On Tue, Aug 1, 2023 at 5:05 PM Guo Ren <guoren@xxxxxxxxxx> wrote:
>
> > The CoRR problem would cause wider problems than this.For this case,
> > do you mean your LL -> LL would be reordered?
> >
> > CPU 0
> >           CPU1
> > LL(2) (set ex-monitor)
> >
> >                 store (break the ex-monitor)
> > LL(1) (reordered instruction set ex-monitor
> > SC(3) (successes ?)
> Sorry for the mail client reformat, I mean:
>
> CPU0  LL(2) (set ex-monitor)
> CPU1  STORE (break the ex-monitor)
> CPU0  LL(1) (reordered instruction set ex-monitor
> CPU0  SC(3) (success?)

No. LL and LL won't reorder because LL implies a memory barrier(though
not acquire semantics).

Regards,
-- 
WANG Rui