Re: [PATCH v7 12/22] x86/decompressor: Call trampoline directly from C code

[Ard Biesheuvel]

On Tue, 1 Aug 2023 at 13:46, Borislav Petkov <bp@xxxxxxxxx> wrote:
>
> On Fri, Jul 28, 2023 at 11:09:06AM +0200, Ard Biesheuvel wrote:
> > Instead of returning to the asm calling code to invoke the trampoline,
> > call it straight from the C code that sets the scene. That way, the
> > struct return type is no longer needed for returning two values, and the
> > call can be made conditional more cleanly in a subsequent patch.
> >
> > This means that all callee save 64-bit registers need to be preserved
> > and restored, as their contents may not survive the legacy mode switch.
> >
> > Acked-by: Kirill A. Shutemov <kirill.shutemov@xxxxxxxxxxxxxxx>
> > Signed-off-by: Ard Biesheuvel <ardb@xxxxxxxxxx>
> > ---
> >  arch/x86/boot/compressed/head_64.S    | 28 +++++++-----------
> >  arch/x86/boot/compressed/pgtable_64.c | 30 ++++++++------------
> >  2 files changed, 23 insertions(+), 35 deletions(-)
> >
> > diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
> > index 1b0c61d1b389fd37..3f38db557112c155 100644
> > --- a/arch/x86/boot/compressed/head_64.S
> > +++ b/arch/x86/boot/compressed/head_64.S
> > @@ -430,24 +430,12 @@ SYM_CODE_START(startup_64)
> >  #endif
> >
> >       /*
> > -      * paging_prepare() sets up the trampoline and checks if we need to
> > -      * enable 5-level paging.
> > -      *
> > -      * paging_prepare() returns a two-quadword structure which lands
> > -      * into RDX:RAX:
> > -      *   - Address of the trampoline is returned in RAX.
> > -      *   - Non zero RDX means trampoline needs to enable 5-level
> > -      *     paging.
> > -      *
> > +      * set_paging_levels() updates the number of paging levels using a
>
> I'd say here "configure paging" or so.
>
> > diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
> > index d66639c961b8eeda..649c51935fdec7ef 100644
> > --- a/arch/x86/boot/compressed/pgtable_64.c
> > +++ b/arch/x86/boot/compressed/pgtable_64.c
> > @@ -16,11 +16,6 @@ unsigned int __section(".data") pgdir_shift = 39;
> >  unsigned int __section(".data") ptrs_per_p4d = 1;
> >  #endif
> >
> > -struct paging_config {
> > -     unsigned long trampoline_start;
> > -     unsigned long l5_required;
> > -};
> > -
> >  /* Buffer to preserve trampoline memory */
> >  static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
> >
> > @@ -29,7 +24,7 @@ static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
> >   * purposes.
> >   *
> >   * Avoid putting the pointer into .bss as it will be cleared between
> > - * paging_prepare() and extract_kernel().
> > + * set_paging_levels() and extract_kernel().
> >   */
> >  unsigned long *trampoline_32bit __section(".data");
> >
> > @@ -106,10 +101,10 @@ static unsigned long find_trampoline_placement(void)
> >       return bios_start - TRAMPOLINE_32BIT_SIZE;
> >  }
> >
> > -struct paging_config paging_prepare(void *rmode)
> > +asmlinkage void set_paging_levels(void *rmode)
>
> So actually "paging_prepare" or "configure_paging" is more to the point
> than setting paging levels. When I see set_paging_levels() I wonder what
> levels are those and I have to look at the code and go, aaah, 5-level vs
> 4-level.
>

configure_5level_paging()? At least, that conveys to some extent that
nothing will happen unless the hardware supports it to begin with.