Re: [PATCH -next V13 1/3] riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACK
From: Guo Ren
Date: Fri Aug 04 2023 - 20:00:38 EST
On Fri, Aug 4, 2023 at 5:41 PM Conor Dooley <conor@xxxxxxxxxx> wrote:
>
> On Fri, Aug 04, 2023 at 11:28:17PM +0200, Jason A. Donenfeld wrote:
> > On Fri, Aug 4, 2023 at 11:28 PM Jason A. Donenfeld <Jason@xxxxxxxxx> wrote:
> > >
> > > Hi Guo,
> > >
> > > On Tue, Jun 13, 2023 at 09:30:16PM -0400, guoren@xxxxxxxxxx wrote:
> > > > From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
> > > >
> > > > Add independent irq stacks for percpu to prevent kernel stack overflows.
> > > > It is also compatible with VMAP_STACK by arch_alloc_vmap_stack.
> > > >
> > > > Tested-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
> > > > Signed-off-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
> > > > Signed-off-by: Guo Ren <guoren@xxxxxxxxxx>
> > > > Cc: Clément Léger <cleger@xxxxxxxxxxxx>
> > >
> > > This patch broke the WireGuard test suite. I've attached the .config
> > > file that it uses. I'm able to fix it by setting CONFIG_EXPERT=y and
> > > CONFIG_IRQ_STACKS=n to essentially reverse the effect of this patch. But
> > > I'd rather not do that.
> > >
> > > Any idea what's up?
>
> Given your config, I suspect you're hitting the issue that is resolved
> by Guo Ren's series:
> https://lore.kernel.org/linux-riscv/20230716001506.3506041-1-guoren@xxxxxxxxxx/
Thx Conor's reply.
>
> Hopefully that's it,
> Conor.
>
> > >
> > > Thanks,
> > > Jason
> >
> > And, err, I guess I failed to describe what's broken exactly. Here's
> > what happens:
> >
> > timeout --foreground 20m qemu-system-riscv64 \
> > -nodefaults \
> > -nographic \
> > -smp 4 \
> > -cpu rv64 -machine virt \
> > -m 256M \
> > -serial stdio \
> > -chardev
> > file,path=/home/zx2c4/Projects/wireguard-linux/tools/testing/selftests/wireguard/qemu/build/riscv64/result,id=result
> > \
> > -device virtio-serial-device -device virtserialport,chardev=result \
> > -no-reboot \
> > -monitor none \
> > -kernel /home/zx2c4/Projects/wireguard-linux/tools/testing/selftests/wireguard/qemu/build/riscv64/kernel/arch/riscv/boot/Image
> >
> > OpenSBI v1.2
> > ____ _____ ____ _____
> > / __ \ / ____| _ \_ _|
> > | | | |_ __ ___ _ __ | (___ | |_) || |
> > | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
> > | |__| | |_) | __/ | | |____) | |_) || |_
> > \____/| .__/ \___|_| |_|_____/|____/_____|
> > | |
> > |_|
> >
> > Platform Name : riscv-virtio,qemu
> > Platform Features : medeleg
> > Platform HART Count : 4
> > Platform IPI Device : aclint-mswi
> > Platform Timer Device : aclint-mtimer @ 10000000Hz
> > Platform Console Device : uart8250
> > Platform HSM Device : ---
> > Platform PMU Device : ---
> > Platform Reboot Device : sifive_test
> > Platform Shutdown Device : sifive_test
> > Firmware Base : 0x80000000
> > Firmware Size : 236 KB
> > Runtime SBI Version : 1.0
> >
> > Domain0 Name : root
> > Domain0 Boot HART : 0
> > Domain0 HARTs : 0*,1*,2*,3*
> > Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
> > Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
> > Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
> > Domain0 Next Address : 0x0000000080200000
> > Domain0 Next Arg1 : 0x000000008fe00000
> > Domain0 Next Mode : S-mode
> > Domain0 SysReset : yes
> >
> > Boot HART ID : 0
> > Boot HART Domain : root
> > Boot HART Priv Version : v1.12
> > Boot HART Base ISA : rv64imafdch
> > Boot HART ISA Extensions : time,sstc
> > Boot HART PMP Count : 16
> > Boot HART PMP Granularity : 4
> > Boot HART PMP Address Bits: 54
> > Boot HART MHPM Count : 16
> > Boot HART MIDELEG : 0x0000000000001666
> > Boot HART MEDELEG : 0x0000000000f0b509
> > [terminates/hangs here]
> >
> > _______________________________________________
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--
Best Regards
Guo Ren