Re: [PATCH v5 13/19] KVM:VMX: Set up interception for CET MSRs

[Yang, Weijiang]

On 8/4/2023 4:16 PM, Chao Gao wrote:
> On Thu, Aug 03, 2023 at 12:27:26AM -0400, Yang Weijiang wrote:
> > Pass through CET MSRs when the associated feature is enabled.
> > Shadow Stack feature requires all the CET MSRs to make it
> > architectural support in guest. IBT feature only depends on
> > MSR_IA32_U_CET and MSR_IA32_S_CET to enable both user and
> > supervisor IBT. Note, This MSR design introduced an architectual
> > limitation of SHSTK and IBT control for guest, i.e., when SHSTK
> > is exposed, IBT is also available to guest from architectual level
> > since IBT relies on subset of SHSTK relevant MSRs.
> >
> > Signed-off-by: Yang Weijiang <weijiang.yang@xxxxxxxxx>
> Reviewed-by: Chao Gao <chao.gao@xxxxxxxxx>
>
> one nit below
Thanks!
> [...]
> > +
> > +	if (kvm_cpu_cap_has(X86_FEATURE_IBT)) {
> > +		incpt = !guest_can_use(vcpu, X86_FEATURE_IBT);
> can you use guest_can_use() or guest_cpuid_has() consistently?
Hmm, the inspiration actually came from Sean:
Re: [RFC PATCH v2 3/6] KVM: x86: SVM: Pass through shadow stack MSRs - Sean Christopherson (kernel.org) <https://lore.kernel.org/all/ZMk14YiPw9l7ZTXP@xxxxxxxxxx/>
it would make the code more reasonable on non-CET platforms.
> > +
> > +		vmx_set_intercept_for_msr(vcpu, MSR_IA32_U_CET,
> > +					  MSR_TYPE_RW, incpt);
> > +		vmx_set_intercept_for_msr(vcpu, MSR_IA32_S_CET,
> > +					  MSR_TYPE_RW, incpt);
> > +	}
> > +}
> > +
> > static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
> > {
> > 	struct vcpu_vmx *vmx = to_vmx(vcpu);
> > @@ -7814,6 +7853,8 @@ static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
> >
> > 	/* Refresh #PF interception to account for MAXPHYADDR changes. */
> > 	vmx_update_exception_bitmap(vcpu);
> > +
> > +	vmx_update_intercept_for_cet_msr(vcpu);
> > }
> >
> > static u64 vmx_get_perf_capabilities(void)
> > --
> > 2.27.0