RE: [PATCH v2] clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op

[Peng Fan]

> Subject: [PATCH v2] clk: imx: composite-8m: fix clock pauses when set_rate
> would be a no-op
> 
> Reconfiguring the clock divider to the exact same value is observed on an
> i.MX8MN to often cause a longer than usual clock pause, probably because
> the divider restarts counting whenever the register is rewritten.
> 
> This issue doesn't show up normally, because the clock framework will take
> care to not call set_rate when the clock rate is the same.
> However, when we reconfigure an upstream clock, the common code will
> call set_rate with the newly calculated rate on all children, e.g.:
> 
>   - sai5 is running normally and divides Audio PLL out by 16.
>   - Audio PLL rate is increased by 32Hz (glitch-free kdiv change)
>   - rates for children are recalculated and rates are set recursively
>   - imx8m_clk_composite_divider_set_rate(sai5) is called with
>     32/16 = 2Hz more
>   - imx8m_clk_composite_divider_set_rate computes same divider as before
>   - divider register is written, so it restarts counting from zero and
>     MCLK is briefly paused, so instead of e.g. 40ns, MCLK is low for 120ns.
> 
> Some external clock consumers can be upset by such unexpected clock
> pauses, so let's make sure we only rewrite the divider value when the value
> to be written is actually different.
> 
> Fixes: d3ff9728134e ("clk: imx: Add imx composite clock")
> Signed-off-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>

Reviewed-by: Peng Fan <peng.fan@xxxxxxx>

Regards,
Peng.