Re: [PATCH 2/2] dt-bindings: clock: intel,cgu-lgm: add mxl,control-gate option

[Yi xin Zhu]

On 31/7/2023 8:59 pm, Florian Eckert wrote:
> This email was sent from outside of MaxLinear.
>
>
> Thanks for your reply,
>
>> You described the desired Linux feature or behavior, not the actual
>> hardware. The bindings are about the latter, so instead you need to
>> rephrase the property and its description to match actual hardware
>> capabilities/features/configuration etc.
> You have correctly identified that this is not a hardware configuration,
> but a driver configuration. Currently, the driver is configured so that
> the gates cannot be switched via the clk subsystem callbacks. When
> registering the data structures from the driver, I have to pass a flag
> GATE_CLK_HW so that the gate is managed by the driver.
>
> I didn't want to always change the source of the driver when it has to
> take
> care of the GATE, so I wanted to map this via the dts.
>
> I have a board support package from Maxlinear for the Lightning Mountain
> Soc
> with other drivers that are not upstream now. Some of them use the
> clock framework some of them does not.
>
> Due to missing documents it is not possible to send these drivers
> upstream.
> Strictly speaking, this is about the gptc and the watchdog.
>
> Since it is a buildin_platform driver, it can also not work via
> module parameters.

Could you please give more details on your target?

In what kind of condition, you want to change the flag?

In LGM SoC,  some gate clocks can be covered by EPU (power management 
module).

that is the reason clock driver introduced the HW/SW flag definition.

However gptc and watchdog are not covered by EPU.  it can only be 
controlled via clock

driver.   So I'm not quite sure the target to change the flag for these 
two clocks.

IMHO,  it's HW fixed in LGM SoC.

>
> Best regards
>
> Florian
>