On 01/08/2023 10:53, Luo Jie wrote:
QCA8386/QCA8084 includes the clock & reset controller that is
accessed by MDIO bus. Two work modes are supported, qca8386 works
as switch mode, qca8084 works as PHY mode.
Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx>
---
.../bindings/clock/qcom,nsscc-qca8k.yaml | 59 ++++++++++
include/dt-bindings/clock/qcom,nsscc-qca8k.h | 102 ++++++++++++++++++
include/dt-bindings/reset/qcom,nsscc-qca8k.h | 76 +++++++++++++
3 files changed, 237 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
create mode 100644 include/dt-bindings/clock/qcom,nsscc-qca8k.h
create mode 100644 include/dt-bindings/reset/qcom,nsscc-qca8k.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
new file mode 100644
index 000000000000..8fb77156070c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nsscc-qca8k.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
+
+maintainers:
+ - Luo Jie <quic_luoj@xxxxxxxxxxx>
+
+description: |
+ Qualcomm NSS clock control module provides the clocks and resets
+ on QCA8386(switch mode)/QCA8084(PHY mode)
+
+ See also::
+ include/dt-bindings/clock/qcom,nsscc-qca8k.h
+ include/dt-bindings/reset/qcom,nsscc-qca8k.h
+
+properties:
+ compatible:
+ const: qcom,nsscc-qca8k
SoC name is before IP block names. See:
Documentation/devicetree/bindings/arm/qcom-soc.yaml
qca8k is not SoC specific. I don't know what you are documenting here,
but if this is a SoC, then follow SoC rules.
If this is not SoC, it confuses me a bit to use GCC binding.
Anyway, this was not tested, as pointed out by bot... Please test the
code before sending.
Best regards,
Krzysztof