Re: [PATCH] perf/smmuv3: Enable HiSilicon Erratum 162001900 quirk for HIP08/09
From: Will Deacon
Date: Fri Aug 11 2023 - 07:17:51 EST
On Wed, Aug 09, 2023 at 06:06:54PM +0800, Yicong Yang wrote:
> diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
> index 25a269d431e4..b854b67b81fc 100644
> --- a/drivers/perf/arm_smmuv3_pmu.c
> +++ b/drivers/perf/arm_smmuv3_pmu.c
> @@ -115,6 +115,7 @@
> #define SMMU_PMCG_PA_SHIFT 12
>
> #define SMMU_PMCG_EVCNTR_RDONLY BIT(0)
> +#define SMMU_PMCG_HARDEN_DISABLE BIT(1)
>
> static int cpuhp_state_num;
>
> @@ -150,6 +151,22 @@ SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_stream_id, config1, 0, 31);
> SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_span, config1, 32, 32);
> SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_enable, config1, 33, 33);
>
> +static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
> + struct perf_event *event, int idx);
> +
> +static inline void smmu_pmu_enable_quirk_hip08_09(struct pmu *pmu)
> +{
> + struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
> + unsigned int idx;
> +
> + for_each_set_bit(idx, smmu_pmu->used_counters, smmu_pmu->num_counters)
> + smmu_pmu_apply_event_filter(smmu_pmu, smmu_pmu->events[idx], idx);
> +
> + writel(SMMU_PMCG_IRQ_CTRL_IRQEN,
> + smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
> + writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
Can you tail-call smmu_pmu_enable() instead of duplicating it here?
> +static inline void smmu_pmu_disable_quirk_hip08_09(struct pmu *pmu)
> +{
> + struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
> + unsigned int idx;
> +
> + /*
> + * The global disable of PMU sometimes fail to stop the counting.
> + * Harden this by writing an invalid event type to each used counter
> + * to forcibly stop counting.
> + */
> + for_each_set_bit(idx, smmu_pmu->used_counters, smmu_pmu->num_counters)
> + writel(0xffff, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
> +
> + writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
> + writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
Same things here, but with smmu_pmu_disable()
Will