Re: [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range

[Abel Vesa]

On Sun, 25 Jun 2023 20:33:39 +0800, Peng Fan (OSS) wrote:
> The SPLL2 on iMX8ULP is different with other frac PLLs, it can
> support VCO from 650Mhz to 1Ghz. According to RM, the MULT is
> using a range from 27 to 54, not some fixed values. If using
> current PLL implementation, some clock rate can't be supported.
> 
> Fix the issue by adding new type for the SPLL2 and use MULT range
> to replace MULT table
> 
> [...]

Applied, thanks!

[1/2] clk: imx: pllv4: Fix SPLL2 MULT range
      commit: 3f0cdb945471f1abd1cf4d172190e9c489c5052a
[2/2] clk: imx: imx8ulp: update SPLL2 type
      commit: 7653a59be8af043adc4c09473975a860e6055ff9

Best regards,
-- 
Abel Vesa <abel.vesa@xxxxxxxxxx>