Re: [PATCH v3 2/2] PCI: pciehp: Clear the optional capabilities in DEVCTL2 on a hot-plug

[Smita Koralahalli]

On 6/28/2023 6:25 AM, Lukas Wunner wrote:
> On Tue, Jun 27, 2023 at 10:38:54AM -0700, Smita Koralahalli wrote:
> > Okay, I see there are no objections except for Bjorn/Jay's comments on
> >
> > "But there could be devices where AtomicOps are nominally supported but
> > untested or broken.."
> >
> > Would this be an issue?
>
> I think you said that BIOS enables AtomicOps on certain AMD machines?
> Or did that observation only apply to 10 Bit tags?
>
> If BIOS does enable AtomicOps, it would be interesting to know which
> logic BIOS follows, i.e. how does it determine whether to set
> AtomicOp Requester Enable on Endpoints?
>
> It would also be interesting to know how far that BIOS has proliferated,
> i.e. how much experience with various Endpoint devices exists in the
> real world.  If it turns out that BIOS has enabled the feature for
> years on a wide range of Endpoints without any issues, I think
> that would render concerns mute that enabling it in the kernel
> might cause regressions.
>
> I don't know why the spec says that "discovery of AtomicOp Requester
> capabilities is outside the scope of this specification".  I imagine
> it would be possible to set AtomicOp Requester Enable, then read it
> to determine whether the bit is now indeed 1 or hard-wired to 0.
> In the latter case, AtomicOp Requester capabilities can be assumed
> to be absent.  So that would be a way to make do without any other
> specific discovery of AtomicOp Requester capabilities.

Sorry for getting back to this very late.

The approach taken by our Platform FW is not as robust as how it is
handled by SW. And also they haven't come across issues for AtomicOps 
similar to 10-bit tags.

Hence, I worked on the approach of reading back the "AtomicOp Requester 
Enable" to determine whether it is indeed 1 or hard-wired to 0.

I came across two issues.

This approach did not eliminate calling pci_enable_atomic_ops_to_root() 
on all drivers as some of them enabled AtomicOp by only checking for 
32-bit and 64-bit Completion capabilities.

And, on internal review I received comments that this approach wouldn't 
help in determining the presence/absence of AtomicOps. PCIe r6.0 sec 
7.5.3.16 [1], states "AtomicOps Requester Enable is permitted to be RW 
even if no AtomicOp Requester capabilities are supported by the Endpoint 
or Root Port", thereby substantiating devices that hardwires this bit to 
'1' is also valid..

I have sent v4 considering all these constraints. Let me know what you 
think.

Thanks,
Smita

> Thanks,
>
> Lukas