Re: [PATCH v2 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe

[Krishna Chaitanya Chundru]

On 8/16/2023 7:10 PM, Dmitry Baryshkov wrote:
> On Wed, 16 Aug 2023 at 16:25, Krishna chaitanya chundru
> <quic_krichai@xxxxxxxxxxx> wrote:
> > PCIe needs to choose the appropriate performance state of RPMH power
> > domain based upon the PCIe gen speed.
> >
> > So let's add the OPP table support to specify RPMH performance states.
> >
> > Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++
> >   1 file changed, 47 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > index 595533a..c77a683 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > @@ -1803,7 +1803,28 @@
> >                          pinctrl-names = "default";
> >                          pinctrl-0 = <&pcie0_default_state>;
> >
> > +                       operating-points-v2 = <&pcie0_opp_table>;
> > +
> >                          status = "disabled";
> > +
> > +                       pcie0_opp_table: opp-table {
> > +                               compatible = "operating-points-v2";
> > +
> > +                               opp-2500000 {
> As a random suggestion: these frequencies are calculated by the
> driver. It might be easier to use opp-level for the PCIe generation
> instead.
>
> This way this OPP entry can become:
>
> opp-1 {
>      opp-level = <1>;
>      required-opps = <&rpmhpd_opp_low_svs>;
> };

This looks good I will try to do in this approach in the next patch if 
there are no other comments.

- KC

> > +                                       opp-hz = /bits/ 64 <2500000>;
> > +                                       required-opps = <&rpmhpd_opp_low_svs>;
> > +                               };
> > +
> > +                               opp-5000000 {
> > +                                       opp-hz = /bits/ 64 <5000000>;
> > +                                       required-opps = <&rpmhpd_opp_low_svs>;
> > +                               };
> > +
> > +                               opp-8000000 {
> > +                                       opp-hz = /bits/ 64 <8000000>;
> > +                                       required-opps = <&rpmhpd_opp_nom>;
> > +                               };
> > +                       };
> >                  };
> >
> >                  pcie0_phy: phy@1c06000 {
> > @@ -1915,7 +1936,33 @@
> >                          pinctrl-names = "default";
> >                          pinctrl-0 = <&pcie1_default_state>;
> >
> > +                       operating-points-v2 = <&pcie1_opp_table>;
> > +
> >                          status = "disabled";
> > +
> > +                       pcie1_opp_table: opp-table {
> > +                               compatible = "operating-points-v2";
> > +
> > +                               opp-2500000 {
> > +                                       opp-hz = /bits/ 64 <2500000>;
> > +                                       required-opps = <&rpmhpd_opp_low_svs>;
> > +                               };
> > +
> > +                               opp-5000000 {
> > +                                       opp-hz = /bits/ 64 <5000000>;
> > +                                       required-opps = <&rpmhpd_opp_low_svs>;
> > +                               };
> > +
> > +                               opp-8000000 {
> > +                                       opp-hz = /bits/ 64 <8000000>;
> > +                                       required-opps = <&rpmhpd_opp_low_svs>;
> > +                               };
> > +
> > +                               opp-16000000 {
> > +                                       opp-hz = /bits/ 64 <16000000>;
> > +                                       required-opps = <&rpmhpd_opp_nom>;
> > +                               };
> > +                       };
> >                  };
> >
> >                  pcie1_phy: phy@1c0f000 {
> > --
> > 2.7.4