Re: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

On Wed, Aug 23, 2023 at 8:42 AM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
>
> On Wed, Aug 23, 2023 at 09:30:48AM +0200, Lorenzo Pieralisi wrote:
> > On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> > > On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> > > <lpieralisi@xxxxxxxxxx> wrote:
> > > > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > > > <lpieralisi@xxxxxxxxxx> wrote:
> > > > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > > >
> > > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > > >   CLKREQ# modes:
> > > > > > >
> > > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > > >
> > > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > > >   this mode (e.g. policy==powersupersave).
> > > > > > >
> > > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > > >   upstream driver implementation that follows adds more details and
> > > > > > >   discerns between (a) and (b).
> > > > > > >
> > > > > > > Signed-off-by: Jim Quinlan <james.quinlan@xxxxxxxxxxxx>
> > > > > > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> > > > > > > ---
> > > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > > >  1 file changed, 9 insertions(+)
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > > >
> > > > > > >    aspm-no-l0s: true
> > > > > > >
> > > > > > > +  brcm,enable-l1ss:
> > > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > >
> > > > > > What does this mean ? I don't think DT properties are supposed
> > > > > > to carry information related to how the OS is configured.
> > > > >
> > > > > The DT setting in question is unrelated to the statement "and the OS
> > > > > has been configured to
> > > > > enable this mode".
> > > > >
> > > > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > > > that you may not get L1SS power savings w/o setting
> > > > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > > > I mentioned that exact term but a reviewer nakked it because
> > > > > apparently DT descriptions should not be OS specific.
> > > > >
> > > > > I am actually open for this to be a command-line option but I wanted to honor
> > > > > what the Raspian OS folks have already done.  RaspianOS already has
> > > > > "brcm,enable-l1ss"
> > > > > set in their DTS files.
> > > >
> > > > This is about the mainline kernel, I don't have any visibility into
> > > > downstream kernels (where that property management was added without DT
> > > > and PCI maintainers supervision).
> > > >
> > > > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > > > the mainline review process even though I understand the position you
> > > > are in.
> > >
> > > Understood, but using the command line has its warts as well; I now recall the
> > > discussion Bjorn and I  had regarding this option.  I'm pretty sure
> > > that upstreaam will not allow the following
> > > possible command line kernel params:
> > >
> > >     brcm,enable-l1ss
> > >     pci=brcm,entable-l1ss
> > >
> > > Bjorn suggested using the  documented but (IMO) obscure  and  rarely
> > > used  format
> > >
> > >     pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> > >
> > > but this is just going in the wrong direction; here's why.  Using the
> > > above iformat s completely dependent on the
> > > PCI "linux-domaiin"  property,  a non-HW related DT property I  might
> > > add.  Since "linux-domain" is already
> > > a valid and well-used  DT property, and the value of  the above
> > > command line format is dependent
> > > on the value of the "linux-domain", why not be consistent and let
> > > "brcm,enable-l1ss" be a Broadcom specific property?
> >
> > I am just asking to add a module_param to the host controller driver.

Adding a module_param, which would have a command line setting such as
"brcm_pcie.enable-l1ss=1"
is for the driver -- we need a per PCIe controller param, as each
controller may have a different setting.

Which brings us to the alternative, a command line param using
pci_dev_str_match() such as

      pci=brcm,enable-l1ss=1:0:0.0

Implementing this would require this AFAICT:

    (1) New file:  drivers/pci/controller/pcie-brcmstb.h
    (2) The "pci.c" file would have to include the above file which I
don't think is a good thing.

>
> A module_param sounds possible to me.  IIRC the bidirectional CLKREQ#
> (config (c)) has been tested and there are no known problems even if
> the OS doesn't enable L1SS.

Ah, I have an update on this.  I was able to communicate with the HW
designer and he explained
that when setting the PCIe core "l1ss bit"  one  loses the benefit  of
Clock Power  Management.  Actually,
let me quote his email so I do not distort his words:

   "If RC is placed in L1SS clkreq mode, may take advantage
    of L1SS power savings, L0s, and L1 power savings, but cannot
    employ Clock Power Management power savings.

    If the RC is placed in "clkreq" clkreq mode, it can only take
    advantage of L0s, L1 power savings, and Clock Power Management
    savings - only omitting L1SS power savings

    The issue is that the Clock Power Management and PM L1 Substates
    are incompatible. The original Clock Power Management feature
    requires the clock to turn on within Tclron=400ns from CLKREQ#
    deassertion, and we feel we need to continue to support products
    that were designed to this requirement. The CLKREQ# deassertion
    to clock turned on requirement with PM L1 Substates was relaxed
    with the addition of the Latency Tolerance Reporting (LTR)
    mechanism. We use the mode bit to distinguish the two modes of
    operation, but currently we aren't looking at whether the RC+EP
    both support the LTR mechanism to make the decision."

I'm not sure if this changes your mind one way or another.

Regards,
Jim Quinlan
Broadcom STB/CM





The only issue (again, IIRC) is that the
> hardware engineer has unspecified reservations about it.
>
> Is there any room to make (c) the default and have a module_param to
> *disable* the L1SS support?  I think the driver knows enough to then
> select (a) or (b) by itself.
>
> Bjorn

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