[PATCH] drm/amdgpu/gfx11: Clean up errors in gfx_v11_0.c

[XueBing Chen]

Fix the following errors reported by checkpatch:

ERROR: that open brace { should be on the previous line
ERROR: spaces required around that '==' (ctx:VxV)
ERROR: space prohibited before that close parenthesis ')'
ERROR: "foo * bar" should be "foo *bar"
ERROR: space required before the open parenthesis '('

Signed-off-by: XueBing Chen <chenxuebing@xxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 5c3db694afa8..6708d3852fe7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -83,8 +83,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin");
 
-static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
-{
+static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = {
 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
@@ -1230,7 +1229,7 @@ static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device
 	int pipe, ucode_id, data_id;
 
 	for (pipe = 0; pipe < 2; pipe++) {
-		if (pipe==0) {
+		if (pipe == 0) {
 			ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0;
 			data_id  = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK;
 		} else {
@@ -2324,7 +2323,7 @@ static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t a
 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
 			(me_hdr->ucode_start_addr_hi << 30) |
-			(me_hdr->ucode_start_addr_lo >> 2) );
+			(me_hdr->ucode_start_addr_lo >> 2));
 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
 			me_hdr->ucode_start_addr_hi>>2);
 
@@ -2508,7 +2507,7 @@ static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev)
 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
 			(me_hdr->ucode_start_addr_hi << 30) |
-			(me_hdr->ucode_start_addr_lo >> 2) );
+			(me_hdr->ucode_start_addr_lo >> 2));
 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
 			me_hdr->ucode_start_addr_hi>>2);
 	}
@@ -2806,7 +2805,7 @@ static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
 			(pfp_hdr->ucode_start_addr_hi << 30) |
-			(pfp_hdr->ucode_start_addr_lo >> 2) );
+			(pfp_hdr->ucode_start_addr_lo >> 2));
 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
 			pfp_hdr->ucode_start_addr_hi>>2);
 
@@ -3025,7 +3024,7 @@ static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
 			(me_hdr->ucode_start_addr_hi << 30) |
-			(me_hdr->ucode_start_addr_lo >> 2) );
+			(me_hdr->ucode_start_addr_lo >> 2));
 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
 			me_hdr->ucode_start_addr_hi>>2);
 
@@ -4202,7 +4201,7 @@ static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev)
 		msleep(100);
 }
 
-static int get_gb_addr_config(struct amdgpu_device * adev)
+static int get_gb_addr_config(struct amdgpu_device *adev)
 {
 	u32 gb_addr_config;
 
@@ -4293,7 +4292,7 @@ static int gfx_v11_0_hw_init(void *handle)
 
 	adev->gfx.is_poweron = true;
 
-	if(get_gb_addr_config(adev))
+	if (get_gb_addr_config(adev))
 		DRM_WARN("Invalid gb_addr_config !\n");
 
 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
-- 
2.17.1