Re: [PATCH v2 2/4] ASoC: es8316: Enable support for MCLK div by 2

[Mark Brown]

On Fri, Aug 25, 2023 at 12:01:33AM +0300, Marian Postevca wrote:

> +/* In at least one AMD laptop the internal timing of the codec goes off
> + * if the MCLK (48Mhz) is not divided by 2. So we will divide all MCLK
> + * frequencies above and equal to 48MHz by 2.
> + */
> +#define MAX_SUPPORTED_MCLK_FREQ 48000000

Given that the datasheet quotes a maximum MCLK of 51.2MHz I suspect that
this is far too high and that performance is degrading well before this
point, it sounds like it just so happens that you noticed issues on a
machine with this MCLK rather than that's based on the spec.  I would
instead suggest applying the MCLK divider in any case where we can do so
and still generate suitable clocking for the rest of the system, or at
least hit 256fs (the datasheet quotes 256/384fs on the front page which
suggests it's targetting 256fs, that'd be a fairly normal number, and
there's mention of 12/24MHz USB clocks being directly usable).  Doing
this should either make no odds or result in better performance.

It's probably also more power efficient to use a lower MCLK, though most
likely the difference is marginal.  The earlier in the clock tree the
divider is applied the lower more of the chip is clocked and all other
things being equal a lower clock usually means lower power.

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