Re: [patch V4 24/41] x86/cpu: Provide cpu_init/parse_topology()

[K Prateek Nayak]

Hello Arjan,

On 8/28/2023 8:04 PM, Arjan van de Ven wrote:
> On 8/28/2023 7:28 AM, K Prateek Nayak wrote:
>>>     - Are these really different between AMD and Intel or is this some
>>>       naming convention issue which needs to be resolved?
>>     They do have different characteristics since, on Sapphire
>>     Rapids, the LLC is at a socket boundary despite having multiple
>>     tiles. (Please correct me if I'm wrong, I'm going off of
>>     llc_id shared in this report by Qiuxu Zhuo -
>>     https://lore.kernel.org/all/20230809161219.83084-1-qiuxu.zhuo@xxxxxxxxx/)
>>
> 
> Sapphire reports itself as 1 tile though (since logically it is) as far as I know
> 

I believe there are some variants with multiple tiles, at least the
following press-release suggests that:

  https://www.intc.com/news-events/press-releases/detail/1598/intel-launches-4th-gen-xeon-scalable-processors-max-series

specifically "... combining up to four Intel 7-built tiles on a single
package, connected using Intel EMIB ...". Perhaps the one from Qiuxu
Zhuo's report does not contain multiple tiles.

But coming back to the characteristics, would it be safe to say "Tile"
would marks the LLC (L3) boundary if 0x1f reports multiple tiles in a
die?
 
--
Thanks and Regards,
Prateek