RE: [PATCH] perf annotate: Add more x86 mov instruction cases

[David Laight]

From: Namhyung Kim
> Sent: 09 September 2023 00:56
> 
> Hi Ian,
> 
> On Thu, Sep 7, 2023 at 11:24 PM Ian Rogers <irogers@xxxxxxxxxx> wrote:
> >
> > On Thu, Sep 7, 2023 at 10:22 PM Namhyung Kim <namhyung@xxxxxxxxxx> wrote:
> > >
> > > Instructions with sign- and zero- extention like movsbl and movzwq were
> > > not handled properly.  As it can check different size suffix (-b, -w, -l
> > > or -q) we can omit that and add the common parts even though some
> > > combinations are not possible.
> > >
> > > Signed-off-by: Namhyung Kim <namhyung@xxxxxxxxxx>
> > > ---
> > >  tools/perf/arch/x86/annotate/instructions.c | 9 ++++++---
> > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/tools/perf/arch/x86/annotate/instructions.c
> b/tools/perf/arch/x86/annotate/instructions.c
> > > index 5f4ac4fc7fcf..5cdf457f5cbe 100644
> > > --- a/tools/perf/arch/x86/annotate/instructions.c
> > > +++ b/tools/perf/arch/x86/annotate/instructions.c
> > > @@ -74,12 +74,15 @@ static struct ins x86__instructions[] = {
> > >         { .name = "movdqa",     .ops = &mov_ops,  },
> > >         { .name = "movdqu",     .ops = &mov_ops,  },
> > >         { .name = "movsd",      .ops = &mov_ops,  },
> > > -       { .name = "movslq",     .ops = &mov_ops,  },
> > >         { .name = "movss",      .ops = &mov_ops,  },
> > > +       { .name = "movsb",      .ops = &mov_ops,  },
> > > +       { .name = "movsw",      .ops = &mov_ops,  },
> > > +       { .name = "movsl",      .ops = &mov_ops,  },
> >
> > In Intel's manual some of these names are "Move Data From String to
> > String" operations, movsb and movsw in particular. These instructions
> > can be used to make simple memcpy loops. Could it be the past omission
> > was deliberate due to the different way the addressing works in the
> > instructions?
> 
> I don't know but in terms of instruction parsing, they are the same
> "MOVE" with two operands.  I'm not aware of anything in perf with
> the operands of these instructions.  So I guess it'd be fine to add
> these instructions even if they have different underlying behaviors.

I'm pretty sure that 'rep movs[bwlq]' (aka while (cx--) *di++ = *si++)
is likely to be missing the memory argument parameters.
There is also 'fun and games' with one variant - iirc 'rep movsd'
what has been used for 64bit, but got hijacked by one of the SIMD sets.

	David

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