Re: [PATCH v2] riscv: dts: thead: set dma-noncoherent to soc bus

[Guo Ren]

On Tue, Sep 12, 2023 at 3:34 PM Jisheng Zhang <jszhang@xxxxxxxxxx> wrote:
>
> riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> dma coherent, so set dma-noncoherent to reflect this fact.
>
> Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
> Tested-by: Drew Fustini <dfustini@xxxxxxxxxxxx>
> ---
>
> Since v1:
>  - rebase on v6.6-rc1
>  - collect Tested-by tag
>
>  arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index ce708183b6f6..ff364709a6df 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -139,6 +139,7 @@ soc {
>                 interrupt-parent = <&plic>;
>                 #address-cells = <2>;
>                 #size-cells = <2>;
> +               dma-noncoherent;
Reviewed-by: Guo Ren <guoren@xxxxxxxxxx>

>                 ranges;
>
>                 plic: interrupt-controller@ffd8000000 {
> --
> 2.40.1
>


-- 
Best Regards
 Guo Ren