Re: [PATCH v3 2/5] arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node

[Tengfei Fan]

在 9/20/2023 6:14 PM, Konrad Dybcio 写道:
> On 9/20/23 08:54, Tengfei Fan wrote:
> > From: Ajit Pandey <quic_ajipan@xxxxxxxxxxx>
> >
> > Add apps_rsc node and cmd_db memory region for sm4450.
> >
> > Signed-off-by: Ajit Pandey <quic_ajipan@xxxxxxxxxxx>
> > Signed-off-by: Tengfei Fan <quic_tengfan@xxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/sm4450.dtsi | 35 ++++++++++++++++++++++++++++
> >   1 file changed, 35 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi 
> > b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> > index c4e5b33f5169..3d9d3b5e9510 100644
> > --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> > @@ -5,6 +5,7 @@
> >   #include <dt-bindings/gpio/gpio.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> >   / {
> >       interrupt-parent = <&intc>;
> > @@ -328,6 +329,18 @@
> >           };
> >       };
> > +    reserved_memory: reserved-memory {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +        ranges;
> > +
> > +        aop_cmd_db_mem: cmd-db@80860000 {
> > +            compatible = "qcom,cmd-db";
> > +            reg = <0x0 0x80860000 0x0 0x20000>;
> > +            no-map;
> > +        };
> > +    };
> > +
> >       soc: soc@0 {
> >           #address-cells = <2>;
> >           #size-cells = <2>;
> > @@ -419,6 +432,28 @@
> >                   status = "disabled";
> >               };
> >           };
> > +
> > +        apps_rsc: rsc@17a00000 {
> > +            compatible = "qcom,rpmh-rsc";
> > +            reg = <0 0x17a00000 0 0x10000>,
> > +                  <0 0x17a10000 0 0x10000>,
> > +                  <0 0x17a20000 0 0x10000>;
> 0x0 for consistency
Hi Konrad,
Yes, I will update "0" to "0x0" for consistency.
> > +            reg-names = "drv-0", "drv-1", "drv-2";
> > +            interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> > +            label = "apps_rsc";
> > +            qcom,tcs-offset = <0xd00>;
> > +            qcom,drv-id = <2>;
> > +            qcom,tcs-config = <ACTIVE_TCS    2>, <SLEEP_TCS     3>,
> > +                      <WAKE_TCS      3>, <CONTROL_TCS   0>;
> You haven't addressed Bjorn's comment about the number of
> CONTROL_TCSes, are you sure 0 is correct?
>
> Konrad
I got confirm from internal power team, setting CONTROL_TCS with 0 is 
correct.


--
Thx and BRs,
Tengfei Fan