Re: [PATCH v10 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes

[Jayesh Choudhary]

Hello Nishanth,

On 27/09/23 17:55, Nishanth Menon wrote:
> On 17:41-20230927, Jayesh Choudhary wrote:
> > From: Siddharth Vadapalli <s-vadapalli@xxxxxx>
> >
> > J784S4 SoC has 4 Serdes instances along with their respective WIZ
> > instances. Add device-tree nodes for them and disable them by default.
> >
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
> > [j-choudhary@xxxxxx: fix serdes_wiz clock order & disable serdes refclk]
> > Signed-off-by: Jayesh Choudhary <j-choudhary@xxxxxx>
> > ---
> >   arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 164 +++++++++++++++++++++
> >   1 file changed, 164 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> > index 6d9a5a91fa75..a0e4d8808693 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> > @@ -6,9 +6,19 @@
> >    */
> >   
> >   #include <dt-bindings/mux/mux.h>
> > +#include <dt-bindings/phy/phy.h>
> > +#include <dt-bindings/phy/phy-ti.h>
> >   
> >   #include "k3-serdes.h"
> >   
> > +/ {
> > +	serdes_refclk: clock-serdes {
> > +		#clock-cells = <0>;
> > +		compatible = "fixed-clock";
> > +		status = "disabled";
>
> Document why disabled. - same for rest of default disabled nodes.

Okay I will add a comment here that the clock is coming from the board
but required here by serdes-wiz node. So keeping it disabled by default.

For serdes and serdes-wiz node, since there are multiple instances,
I will mention in the commit message that the nodes are incomplete
and phy link is added in the board file. Hence disabled by default.

Thanks,
-Jayesh

> > +	};
> > +};
> > +
> >   &cbass_main {
> >   	msmc_ram: sram@70000000 {
> >   		compatible = "mmio-sram";
> > @@ -709,6 +719,160 @@ main_sdhci1: mmc@4fb0000 {
> >   		status = "disabled";
> >   	};
> >   
> > +	serdes_wiz0: wiz@5060000 {
> > +		compatible = "ti,j784s4-wiz-10g";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
> > +		clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
> > +		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> > +		assigned-clocks = <&k3_clks 404 6>;
> > +		assigned-clock-parents = <&k3_clks 404 10>;
> > +		num-lanes = <4>;
> > +		#reset-cells = <1>;
> > +		#clock-cells = <1>;
> > +		ranges = <0x5060000 0x00 0x5060000 0x10000>;
> > +		status = "disabled";
> > +
> > +		serdes0: serdes@5060000 {
> > +			compatible = "ti,j721e-serdes-10g";
> > +			reg = <0x05060000 0x010000>;
> > +			reg-names = "torrent_phy";
> > +			resets = <&serdes_wiz0 0>;
> > +			reset-names = "torrent_reset";
> > +			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> > +				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> > +			clock-names = "refclk", "phy_en_refclk";
> > +			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> > +					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> > +					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> > +			assigned-clock-parents = <&k3_clks 404 6>,
> > +						 <&k3_clks 404 6>,
> > +						 <&k3_clks 404 6>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			#clock-cells = <1>;
> > +			status = "disabled";
> > +		};
> > +	};
> > +
> > +	serdes_wiz1: wiz@5070000 {
> > +



>