Re: [PATCH 1/1] clk: socfpga: gate: Fix of by factor 2 for serial console

[Stephen Boyd]

Quoting Benedikt Spranger (2023-10-05 11:32:23)
> On Thu, 5 Oct 2023 13:34:01 +0200
> Maxime Ripard <mripard@xxxxxxxxxx> wrote:
> 
> > Hi,
> > 
> > On Thu, Oct 05, 2023 at 11:59:27AM +0200, Benedikt Spranger wrote:
> > > Commit 9607beb917df ("clk: socfpga: gate: Add a determine_rate
> > > hook") introduce a specific determine_rate hook. As a result the
> > > calculated clock for the serial IP is off by factor 2 after that
> > > i.e. if the system configures a baudrate of 115200 it is set
> > > physicaly to 57600.  
> > 
> > Where is that factor 2 coming from?
> In drivers/tty/serial/8250/8250_dw.c p->uartclk is set twice as high,
> as it should be: 
> 
> dw8250_set_termios() is called and rate is evaluated to 20000000 in the
> bad and 10000000 in the good case. As a result p->uartclk is set to
> 20000000 in the bad case.
> 
> > > Change the determine_rate hook to the reparent variant
> > > __clk_mux_determine_rate() to fix the issue.  
> > 
> > It's also not clear to me why that would fix anything. This patch
> > should only make the old behaviour explicit, could you expand a bit
> > on what happens?
> Booting the kernel with console=ttyS0,115200 result in a corrupted
> character output. Setting the serial terminal application to 57600
> make the serial console working.
> 
> I dug deeper and added some debug output (see patch below):

What's your analysis?

Does this patch also fix it?

---8<---
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 8dd601bd8538..b3400d2d8128 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -173,6 +173,7 @@ void __init socfpga_gate_init(struct device_node *node)
 	if (init.num_parents < 2) {
 		ops->get_parent = NULL;
 		ops->set_parent = NULL;
+		ops->determine_rate = NULL;
 	}
 
 	init.parent_names = parent_name;