[irqchip: irq/irqchip-fixes] dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property

[irqchip-bot for Lorenzo Pieralisi]

The following commit has been merged into the irq/irqchip-fixes branch of irqchip:

Commit-ID:     5e5c636c69bdba04033161bbb111fbb6f1f6661e
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/5e5c636c69bdba04033161bbb111fbb6f1f6661e
Author:        Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>
AuthorDate:    Fri, 06 Oct 2023 14:59:25 +02:00
Committer:     Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Sat, 07 Oct 2023 12:47:12 +01:00

dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property

The GIC v3 specifications allow redistributors and ITSes interconnect
ports used to access memory to be wired up in a way that makes the
respective initiators/memory observers non-coherent.

Add the standard dma-noncoherent property to the GICv3 bindings to
allow firmware to describe the redistributors/ITSes components and
interconnect ports behaviour in system designs where the redistributors
and ITSes are not coherent with the CPU.

Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20231006125929.48591-2-lpieralisi@xxxxxxxxxx
---
 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
index 2bc3847..0f4a062 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
@@ -106,6 +106,12 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     maximum: 4096
 
+  dma-noncoherent:
+    description:
+      Present if the GIC redistributors permit programming shareability
+      and cacheability attributes but are connected to a non-coherent
+      downstream interconnect.
+
   msi-controller:
     description:
       Only present if the Message Based Interrupt functionality is
@@ -193,6 +199,12 @@ patternProperties:
       compatible:
         const: arm,gic-v3-its
 
+      dma-noncoherent:
+        description:
+          Present if the GIC ITS permits programming shareability and
+          cacheability attributes but is connected to a non-coherent
+          downstream interconnect.
+
       msi-controller: true
 
       "#msi-cells":