Re: [PATCH v3 3/4] clk: renesas: rzg2l: add a divider clock for RZ/G3S

[Geert Uytterhoeven]

On Fri, Oct 6, 2023 at 12:40 PM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> Add a divider clock driver for RZ/G3S. This will be used in RZ/G3S
> by SDHI, SPI, OCTA, I, I2, I3, P0, P1, P2, P3 core clocks.
> The divider has some limitation for SDHI, OCTA and SPI clocks:
> - SDHI div cannot be 1 if parent rate is 800MHz
> - OCTA, SPI div cannot be 1 if parent rate is 400MHz
> For these clocks a notifier could be registered from platform specific
> clock driver and proper actions are taken before clock rate is changed,
> if needed.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> ---
>
> Changes in v3:
> - adjusted commit message to specifies that divider has limitations also
>   for SPI clock
> - s/SD div/SDHI div in commit message
> - return proper code from notifier
> - used CPG_WEN_BIT where possible notifier and set explicitily 1 in div
>   notifier
> - removed rzg3s_div_clk_is_rate_valid() and all its occurencies: it was
>   not needed in rzg3s_div_clk_set_rate()
> - .round_rate was replaced by .determine_rate for the introduced divider
> - initialized max variable in rzg3s_cpg_div_clk_register()
> - introduced struct div_hw_data::max_rate to specify from the SoC-specific
>   drivers the maximum available rate for divider that will be requested
>   when a rate higher than this one is requested
> - removed bitmask variable from notifier and rzg3s_div_clk_set_rate()
> - added max_rate to DEF_G3S_DIV() macro
> - tested on RZ/G2L and RZ/G3S

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk-for-v6.7.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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when I'm talking to journalists I just say "programmer" or something like that.
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