Re: [PATCH 1/1] clk: socfpga: gate: Fix of by factor 2 for serial console

[Benedikt Spranger]

On Wed, 11 Oct 2023 11:17:22 +0200
Maxime Ripard <mripard@xxxxxxxxxx> wrote:

Hi,

> Could you test that patch?
The system booted fine. Serial console is working as expected

> ----8<----
> 
> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
> index 8dd601bd8538..486a4d84e418 100644
> --- a/drivers/clk/socfpga/clk-gate.c
> +++ b/drivers/clk/socfpga/clk-gate.c
> @@ -87,10 +87,8 @@ static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
>  	return 0;
>  }
> 
> -static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
> -	unsigned long parent_rate)
> +static u32 socfpga_clk_get_div(struct socfpga_gate_clk *socfpgaclk)
>  {
> -	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
>  	u32 div = 1, val;
> 
>  	if (socfpgaclk->fixed_div)
> @@ -105,12 +103,33 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>  			div = (1 << val);
>  	}
> 
> +	return div;
> +}
> +
> +static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
> +					     unsigned long parent_rate)
> +{
> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> +	u32 div = socfpga_clk_get_div(socfpgaclk);
> +
>  	return parent_rate / div;
>  }
> 
> +
> +static int socfpga_clk_determine_rate(struct clk_hw *hw,
                                                       *hwclk,
> +				      struct clk_rate_request *req)
> +{
> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> +	u32 div = socfpga_clk_get_div(socfpgaclk);
> +
> +	req->rate = req->best_parent_rate / div;
> +
> +	return 0;
> +}
> +
>  static struct clk_ops gateclk_ops = {
>  	.recalc_rate = socfpga_clk_recalc_rate,
> -	.determine_rate = clk_hw_determine_rate_no_reparent,
> +	.determine_rate = socfpga_clk_determine_rate,
>  	.get_parent = socfpga_clk_get_parent,
>  	.set_parent = socfpga_clk_set_parent,
>  };

Regards
    Benedikt Spranger