Re: [tip: x86/urgent] x86/cpu: Fix AMD erratum #1485 on Zen4-based CPUs

[Borislav Petkov]

On Wed, Oct 11, 2023 at 11:28:26PM +0200, Ingo Molnar wrote:
> While in reality:
> 
>    Zen 2 == Fam 17h
>    Zen 4 == Fam 19h

If only were that easy...

family 0x17 is Zen1 and 2, family 0x19 is spread around Zen 3 and 4.

> 
> So it's confusing to list these separately and out of order.
> 
> So in resolving the conflict in perf/core I updated this section to read:
> 
>   /* Fam 19h (Zen 4) MSRs */

That's wrong.

>   #define MSR_F19H_UMC_PERF_CTL		0xc0010800
>   #define MSR_F19H_UMC_PERF_CTR		0xc0010801
> 
>   #define MSR_ZEN4_BP_CFG		0xc001102e
>   #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
> 
>   /* Fam 17h (Zen 2) MSRs */

Ditto.

> This doesn't change the definitions themselves, only merges the comments 
> and the sections, (to keep the Git conflict resolution non-evil), but 
> arguably once perf/core goes upstream, we should probably unify the naming 
> to follow the existing nomenclature, which is, starting at around F15H, the 
> following:
> 
>    MSR_F15H_
>    MSR_F16H_
>    MSR_F17H_
>    MSR_F19H_
> 
> Or are the MSRs named ZEN2 and ZEN4 in AMD SDMs, which we should follow?

See above. The MSRs are per Zen generation while the family is per
family. Yes, it is confusing. :-\

IOW, you want to have this as the end product:

/* Zen4 */
#define MSR_ZEN4_BP_CFG                 0xc001102e
#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5

/* Fam 19h MSRs */
#define MSR_F19H_UMC_PERF_CTL           0xc0010800
#define MSR_F19H_UMC_PERF_CTR           0xc0010801

/* Zen 2 */
#define MSR_ZEN2_SPECTRAL_CHICKEN       0xc00110e3
#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT   BIT_ULL(1)

/* Fam 17h MSRs */
#define MSR_F17H_IRPERF			0xc00000e9

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette