Re: [PATCH] x86/mm: fix pg_level_to_pfn for 5-level paging mode.

[Ingo Molnar]

* Ashish Kalra <Ashish.Kalra@xxxxxxx> wrote:

> From: Ashish Kalra <ashish.kalra@xxxxxxx>
> 
> Add support for 5-level paging in pg_level_to_pfn().
> 
> Signed-off-by: Ashish Kalra <ashish.kalra@xxxxxxx>
> ---
>  arch/x86/mm/mem_encrypt_amd.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c
> index 6faea41e99b6..45914568596a 100644
> --- a/arch/x86/mm/mem_encrypt_amd.c
> +++ b/arch/x86/mm/mem_encrypt_amd.c
> @@ -267,6 +267,10 @@ static unsigned long pg_level_to_pfn(int level, pte_t *kpte, pgprot_t *ret_prot)
>  		pfn = pud_pfn(*(pud_t *)kpte);
>  		prot = pud_pgprot(*(pud_t *)kpte);
>  		break;
> +	case PG_LEVEL_512G:
> +		pfn = p4d_pfn(*(p4d_t *)kpte);
> +		prot = p4d_pgprot(*(p4d_t *)kpte);
> +		break;

Mind explaining what happens if we don't have this fix, how you found it, 
which users are expected to be affected by it, whether that's the full 
known extent of 5-level paging support deficiencies in mem_encrypt_amd.c, 
etc?

In addition to such patches being much easier on the eyes, it also helps 
maintainers prioritize patches.

Thanks,

	Ingo