Re: [PATCH] iommu/amd: Do not flush IRTE when only updating isRun and destination fields

[Suthikulpanit, Suravee]

On 10/17/2023 9:51 PM, Maxim Levitsky wrote:
> У вт, 2023-10-17 у 09:42 -0500, Suravee Suthikulpanit пише:
> > According to the recent update in the AMD IOMMU spec [1], the IsRun and
> > Destination fields of the Interrupt Remapping Table Entry (IRTE) are not
> > cached by the IOMMU hardware.
> Is that true for all AMD hardware that supports AVIC? E.g Zen1/Zen2 hardware?

This is true for all AVIC/x2AVIC-capable IOMMU hardware in the past.

> Is there a chance that this will cause a similar errata to the is_running
> errata that Zen2 cpus have?

Please let me check on this and get back.

> > Therefore, do not issue the INVALIDATE_INTERRUPT_TABLE command when
> > updating IRTE[IsRun] and IRTE[Destination] when IRTE[GuestMode]=1, which
> > should help improve IOMMU AVIC/x2AVIC performance.
> >
> > References:
> > [1] AMD IOMMU Spec Revision (Rev 3.08-PUB)
> > (Link:https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_IOMMU.pdf)
> Looks like the link is broken.

The link above is the default location for AMD IOMMU spec, (which is 
currently being fixed). In the mean time, here is the temporary link to 
the latest document.

(https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_07_PUB.pdf)

Thanks,
Suravee