Re: [PATCH v2 01/11] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks

[Konrad Dybcio]

On 10/19/23 02:16, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2023-09-15 05:19:56)
> > On 14.09.2023 08:59, Kathiravan Thirumoorthy wrote:
> > > GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based
> > > on the request from dependent clocks. Doing so will result in the
> > > unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL
> > > clocks.
> > >
> > > Cc: stable@xxxxxxxxxxxxxxx
> > > Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
> > > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@xxxxxxxxxxx>
> > > ---
> > Stephen, do you think there should be some sort of error
> > or at least warning thrown when SET_RATE_PARENT is used with
> > RO ops?
>
> Sure? How would that be implemented?
drivers/clk/clk.c : static void clk_change_rate()

if (!skip_set_rate && core->ops->set_rate)
	core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);

->

if (!skip_set_rate) {
	if (core->ops->set_rate)
		core->ops->set_rate(core->hw, core->new_rate,
				    best_parent_rate);
	else
		pr_err("bad idea");
}

Konrad