Re: [kvm-unit-tests Patch 4/5] x86: pmu: Support validation for Intel PMU fixed counter 3

[Mi, Dapeng]

On 10/25/2023 3:05 AM, Jim Mattson wrote:
> On Tue, Oct 24, 2023 at 12:51 AM Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx> wrote:
> > Intel CPUs, like Sapphire Rapids, introduces a new fixed counter
> > (fixed counter 3) to counter/sample topdown.slots event, but current
> > code still doesn't cover this new fixed counter.
> >
> > So add code to validate this new fixed counter.
> Can you explain how this "validates" anything?


I may not describe the sentence clearly. This would validate the fixed 
counter 3 can count the slots event and get a valid count in a 
reasonable range. Thanks.


> > Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
> > ---
> >   x86/pmu.c | 3 ++-
> >   1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/x86/pmu.c b/x86/pmu.c
> > index 1bebf493d4a4..41165e168d8e 100644
> > --- a/x86/pmu.c
> > +++ b/x86/pmu.c
> > @@ -46,7 +46,8 @@ struct pmu_event {
> >   }, fixed_events[] = {
> >          {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N},
> >          {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N},
> > -       {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N}
> > +       {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N},
> > +       {"fixed 4", MSR_CORE_PERF_FIXED_CTR0 + 3, 1*N, 100*N}
> >   };
> >
> >   char *buf;
> > --
> > 2.34.1