From: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>[...]
Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for
SC8380XP SoC, describing the CPUs, GCC and RPMHCC clock controllers,
geni UART, interrupt controller, TLMM, reserved memory, interconnects,
SMMU and LLCC nodes.
Co-developed-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
Signed-off-by: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
Co-developed-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
---
+&tlmm {It would be really cool if you added an explanation on why these
+ gpio-reserved-ranges = <33 3>, <44 4>, <238 1>;
+ compatible = "qcom,oryon";Again, this compatible won't fly unless all of these cores
+ reg = <0x0 0x0>;I'm not sure if L1 is supposed to be described in the DT,
+ enable-method = "psci";
+ next-level-cache = <&L1_0>;
+
+ L1_0: l1-cache {
+ compatible = "cache";
+ next-level-cache = <&L2_0>;cache-level?
+
+ L2_0: l2-cache-0 {
+ compatible = "cache";
+ memory@80000000 {That contradicts the comment you made above. Plus, 2 GiB seems a
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0x80000000>;
+ gunyah_hyp_mem: gunyah-hyp-region@80000000 {you can probably strip the "-region" part, as this is implied by
+ pld_pep_mem: pld-pep-region@81f30000 {What's PLD?
+ av1_encoder_mem: av1-encoder-region@8e900000 {Is AV1enc hardware separate from iris?
+ gcc: clock-controller@100000 {The address part of reg should be padded to 8 hex digits.
+ compatible = "qcom,sc8380xp-gcc";
+ reg = <0 0x100000 0 0x200000>;
+QCOM_ICC_TAG_ALWAYS would be nicer than 0 (see sa8775p)
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
+One space after and before '='
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,