Re: [POC][RFC][PATCH v2] sched: Extended Scheduler Time Slice

[Mathieu Desnoyers]

On 2023-10-26 07:14, Steven Rostedt wrote:
> On Thu, 26 Oct 2023 12:59:44 +0200
> Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
>
> > On Wed, Oct 25, 2023 at 11:54:13PM -0400, Steven Rostedt wrote:
> >
> > >   static void extend(void)
> > >   {
> > > 	rseq_map.cr_flags = 1;
> > >   }
> > >
> > >   static void unextend(void)
> > >   {
> > > 	unsigned long prev;
> > >
> > > 	prev = xchg(&rseq_map.cr_flags, 0);
> >
> > So you complain about overhead and then you add one of the most
> > expensive ops possible here? xchg has an implicit LOCK prefix and you
> > really don't need LOCK prefix here.
>
> Peter, this is the user space side, where I cut and pasted the code from
> the file I attached.
>
> That has:
>
> static inline unsigned long
> xchg(volatile unsigned *ptr, unsigned new)
> {
>          unsigned ret = new;
>
> 	asm volatile("xchg %b0,%1"

which has an implicit lock prefix (xchg with a memory operand is a 
special-case):

Quoting Intel manual:

"If a memory operand is referenced, the processor’s locking protocol is 
automatically implemented for the duration of the exchange operation, 
regardless of the presence or absence of the LOCK prefix or of the value 
of the IOPL. (See the LOCK prefix description in this chapter for more 
information on the locking protocol.)"

Thanks,

Mathieu


> 		     : "+r"(ret), "+m"(*(ptr))
> 		     : : "memory");
>          return ret;
> }
>
> -- Steve
>
>
> > > 	if (prev & 2) {
> > > 		tracefs_printf(NULL, "Yield!\n");
> > > 		sched_yield();
> > > 	}
> > >   }

--
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com