Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node

From: Mrinmay Sarkar
Date: Fri Nov 10 2023 - 13:23:54 EST



On 11/8/2023 3:24 AM, Konrad Dybcio wrote:


On 11/7/23 19:37, Andrew Halaney wrote:
On Tue, Nov 07, 2023 at 06:34:53PM +0530, Mrinmay Sarkar wrote:
Add ep pcie dtsi node for pcie1 controller found on sa8775p platform.
It supports gen4 and x4 link width. Limiting the speed to Gen3 due to
stability issues.

I wouldn't mind a bit more information on what "stability" issues
entails! I'm a sucker for details in a commit message.
Yep, giving us a bit more than "doesnt work" may help us help you!
Actually if I enable gen4 some time I am getting link down and sometime
link getting establish at gen1. I am not getting stable gen4, may be we
need to program some register to get stable gen4 that I am checking.
+
+        interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
Looks like the indentation is off?

+
+        interrupt-names = "global", "doorbell", "dma";
+
+        interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
+                <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;

I keep seeing Konrad requesting that we use the #define instead of a raw
number 0, i.e. something like QCOM_ICC_TAG_ALWAYS (although if I'm
reading that correctly QCOM_ICC_TAG_ALWAYS doesn't evaluate to 0, so
make sure you pick the appropriate one).
No it doesn't, but if you look at the code, tag being non-existent
assigns QCOM_ICC_TAG_ALWAYS which is a workaround for DTBs from back
when interconnect tags were not a thing


+        interconnect-names = "pcie-mem", "cpu-pcie";

This is nitpicky, but unless someone told you to do the whitespace
between some of these properties I'd get more consistent. i.e. reg and
reg-names has no newline between them, but clocks and clock-names does,
and then interconnects/interconnect-names does not.
:)
I don't think there is any rule to add those white spaces, in next patch
I will align these white spaces with other pcie nodes.

Konrad

Thanks,
Mrinmay