Re: [PATCH 1/1] iommu/vt-d: Fix incorrect cache invalidation for mm notification

[Jason Gunthorpe]

On Fri, Nov 17, 2023 at 05:09:33PM +0800, Lu Baolu wrote:
> Commit 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when
> invalidating TLBs") moved the secondary TLB invalidations into the TLB
> invalidation functions to ensure that all secondary TLB invalidations
> happen at the same time as the CPU invalidation and added a flush-all
> type of secondary TLB invalidation for the batched mode, where a range
> of [0, -1UL) is used to indicates that the range extends to the end of
> the address space.
> 
> However, using an end address of -1UL caused an overflow in the Intel
> IOMMU driver, where the end address was rounded up to the next page.
> As a result, both the IOTLB and device ATC were not invalidated correctly.
> 
> Add a flush all helper function and call it when the invalidation range
> is from 0 to -1UL, ensuring that the entire caches are invalidated
> correctly.
> 
> Fixes: 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when invalidating TLBs")
> Cc: stable@xxxxxxxxxxxxxxx
> Cc: Huang Ying <ying.huang@xxxxxxxxx>
> Cc: Alistair Popple <apopple@xxxxxxxxxx>
> Tested-by: Luo Yuzhang <yuzhang.luo@xxxxxxxxx> # QAT
> Tested-by: Tony Zhu <tony.zhu@xxxxxxxxx> # DSA
> Signed-off-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
> ---
>  drivers/iommu/intel/svm.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)

Reviewed-by: Jason Gunthorpe <jgg@xxxxxxxxxx>

This should go to -rc

Jason