Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core

[Mark Brown]

On Sat, Nov 18, 2023 at 07:24:39PM +0530, Amit Kumar Mahapatra wrote:
> AMD-Xilinx GQSPI controller has two advanced mode that allows the
> controller to consider two flashes as one single device.

This breaks an x86 allmodconfig build:

/build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c: In function ‘cs35l56_hda_spi
_probe’:
/build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c:32:52: error: passing argumen
t 2 of ‘cs35l56_hda_common_probe’ makes integer from pointer without a cast [-We
rror=int-conversion]
   32 |         ret = cs35l56_hda_common_probe(cs35l56, spi->chip_select);
      |                                                 ~~~^~~~~~~~~~~~~
      |                                                    |
      |                                                    u8 * {aka unsigned ch
ar *}
In file included from /build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c:12:
/build/stage/linux/sound/pci/hda/cs35l56_hda.h:45:63: note: expected ‘int’ but a
rgument is of type ‘u8 *’ {aka ‘unsigned char *’}
   45 | int cs35l56_hda_common_probe(struct cs35l56_hda *cs35l56, int id);
      |                                                           ~~~~^~

Attachment: signature.asc
Description: PGP signature