Re: [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register

[Geert Uytterhoeven]

On Mon, 20 Nov 2023, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes
> the operation to clear interrupts through the ISCR register as follows:
>
> [Write operation]
> When "Falling-edge detection", "Rising-edge detection" or
> "Falling/Rising-edge detection" is set in IITSR:
> - In case ISTAT is 1
> 	0: IRQn interrupt detection status is cleared.
> 	1: Invalid to write.
> - In case ISTAT is 0
> 	Invalid to write.
>
> When “Low-level detection” is set in IITSR.:
> 	Invalid to write.
>
> Take the interrupt type into account when clearing interrupts through
> the ISCR register to avoid writing the ISCR when interrupt type is
> level.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds