On Tue, Nov 14, 2023 at 09:10:33AM +0800, Lu Baolu wrote:
diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.hIs it racey?
index 65d37a138c75..ce030c5b5772 100644
--- a/drivers/iommu/intel/iommu.h
+++ b/drivers/iommu/intel/iommu.h
@@ -602,6 +602,9 @@ struct dmar_domain {
*/
u8 dirty_tracking:1; /* Dirty tracking is enabled */
u8 nested_parent:1; /* Has other domains nested on it */
+ u8 has_mappings:1; /* Has mappings configured through
+ * iommu_map() interface.
+ */
The other option is to make iommfd do this and forbid it from
switching the enforce_cache_coherency if the IOAS has any maps
attached. We can get the correct locking at that point.
AMD has the same issue if it ever wants to implement its per-PTE bit