[PATCH v1 11/16] dt-bindings: clock: Add StarFive JH8100 System-South-West clock and reset generator
From: Sia Jee Heng
Date: Wed Dec 06 2023 - 06:52:51 EST
Add bindings for the System-South-West clock and reset generator
(SYSCRG-SW) on JH8100 SoC.
Signed-off-by: Sia Jee Heng <jeeheng.sia@xxxxxxxxxxxxxxxx>
Reviewed-by: Ley Foon Tan <leyfoon.tan@xxxxxxxxxxxxxxxx>
---
.../clock/starfive,jh8100-syscrg-sw.yaml | 66 +++++++++++++++++++
.../dt-bindings/clock/starfive,jh8100-crg.h | 14 ++++
.../dt-bindings/reset/starfive,jh8100-crg.h | 10 +++
3 files changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml
new file mode 100644
index 000000000000..8bd41af040b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-sw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 System-South-West Clock And Reset Generator
+
+maintainers:
+ - Sia Jee Heng <jeeheng.sia@xxxxxxxxxxxxxxxx>
+
+properties:
+ compatible:
+ const: starfive,jh8100-syscrg-sw
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB_BUS clock from SYSCRG
+ - description: VDEC_ROOT clock from SYSCRG
+ - description: FLEXNOC1 clock from SYSCRG
+
+ clock-names:
+ items:
+ - const: sys_clk_apb_bus
+ - const: sys_clk_vdec_root
+ - const: sys_clk_flexnoc1
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jh8100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+ clock-controller@12720000 {
+ compatible = "starfive,jh8100-syscrg-sw";
+ reg = <0x12720000 0x10000>;
+ clocks = <&syscrg SYSCRG_CLK_APB_BUS>,
+ <&syscrg SYSCRG_CLK_VDEC_ROOT>,
+ <&syscrg SYSCRG_CLK_FLEXNOC1>;
+ clock-names = "sys_clk_apb_bus",
+ "sys_clk_vdec_root",
+ "sys_clk_flexnoc1";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
index b30ccd16a802..3ce0b9ec66be 100644
--- a/include/dt-bindings/clock/starfive,jh8100-crg.h
+++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
@@ -344,4 +344,18 @@
#define SYSCRG_NE_CLK_SMBUS0_ICG_EN 174
#define SYSCRG_NE_CLK_END 175
+
+/* SYSCRG_SW_CLK */
+#define SYSCRG_SW_CLK_JPEG_AXI 0
+#define SYSCRG_SW_CLK_VC9000DJ_AXI 1
+#define SYSCRG_SW_CLK_VC9000DJ_VDEC 2
+#define SYSCRG_SW_CLK_VC9000DJ_APB 3
+#define SYSCRG_SW_CLK_VDEC_AXI 4
+#define SYSCRG_SW_CLK_VC9000D_AXI 5
+#define SYSCRG_SW_CLK_VC9000D_VDEC 6
+#define SYSCRG_SW_CLK_VC9000D_APB 7
+#define SYSCRG_SW_CLK_JPEG_ICG_EN 8
+#define SYSCRG_SW_CLK_VDEC_ICG_EN 9
+
+#define SYSCRG_SW_CLK_END 10
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
index 7626da648686..55209382e00e 100644
--- a/include/dt-bindings/reset/starfive,jh8100-crg.h
+++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
@@ -96,4 +96,14 @@
#define SYSCRG_NE_RSTN_DUBHE_TVSENSOR 49
#define SYSCRG_NE_RESET_NR_RESETS 50
+
+/*
+ * syscrg_sw: assert0
+ */
+#define SYSCRG_SW_RSTN_PRESETN 0
+#define SYSCRG_SW_RSTN_VC9000DJ 1
+#define SYSCRG_SW_RSTN_VC9000D 2
+#define SYSCRG_SW_RSTN_DDR_TVSENSOR 3
+
+#define SYSCRG_SW_RESET_NR_RESETS 4
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
--
2.34.1