RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs
From: James Tai [戴志峰]
Date: Wed Dec 06 2023 - 10:08:11 EST
Hi Krzysztof,
>>>>>>>>> + interrupts-extended:
>>>>>>>>
>>>>>>>> interrupts instead.
>>>>>>>>
>>>>>>>> Anyway, you must describe the items. Why this is not fixed but
>flexible?
>>>>>>>> Hardware has different number of pins? That's unlikely.
>>>>>>>>
>>>>>>> I will replace it with 'interrupts'. Since our Interrupt
>>>>>>> controller architecture doesn't involve multiple interrupt sources, using
>'interrupts'
>>>>> should suffice.
>>>>>>>
>>>>>>
>>>>>> Due to changes in hardware design, some peripheral interrupts pin
>>>>>> initially
>>>>> connected to the Realtek interrupt controller were redirected to the GIC.
>>>>>> However, the associated fields and statuses in the Realtek
>>>>>> interrupt controller
>>>>> registers were not removed.
>>>>>> As a result, these interrupts cannot be cleared by peripheral
>>>>>> register, and their
>>>>> status clearing is still needing the Realtek interrupt controller
>>>>> driver to
>>> manage.
>>>>>>
>>>>>> That's why flexibility is necessary.
>>>>>
>>>>> This does not explain why this is not fixed per variant.
>>>>>
>>>>
>>>> Does the definition of "fixed" you mentioned refer to fixed
>>>> interrupt pins? If not, could you please give me an example and let
>>>> me know what you mean by "fixed"?
>>>
>>> Number of the interrupts per each device or variant should be
>>> strictly defined, not variable.
>>
>> Thank you for your explanation.
>>
>> The DHC platforms contain two interrupt controllers, each handling peripheral
>device interrupts in the two power domains.
>> While each has a fixed IRQ numbers, the specific IRQ varies depending on the
>>platform.
>
>Srsly, what "specific IRQ" has anything to do with "number of interrupts per
>each device or variant"?
Each Realtek interrupt controller is assigned a fixed IRQ, which gathers interrupts from peripheral devices such as i2c, spi, ethernet phy, timer, uart, watchdog, rtc, pwm, etc.
Due to modifications in the hardware circuit, certain peripheral device interrupts including watchdog, rtc, uart1, and uart2 are now redirected to the GIC.
Consequently, these devices cannot clear interrupt statuses through their own registers. To resolve this, we manage their interrupts through the Realtek interrupt controller.
This results in a variation in the number of IRQs registered by the interrupt controllers of ISO (isolation) and MSIC (miscellaneous).
In the DTS examples provided in the initial patch release, IRQs 41 and 42 are assigned to the Realtek interrupt controller.
As watchdog, rtc, uart1, and uart2 interrupts no longer use IRQs 41 or 42, their IRQs (0, 39, 89, 90) are assigned to be registered by the Realtek interrupt controller.
Fixed IRQs:
- 41: peripheral devices (iso power domain)
- 42: peripheral devices (misc power domain)
Specific IRQs:
- 0: watchdog (iso power domain)
- 39: rtc (misc power domain)
- 89: uart1 (misc power domain)
- 90: uart2 (misc power domain)
Examples(v1 patches):
iso_irq_mux: iso_irq_mux@40 {
compatible = "realtek,rtd1319-intc-iso";
reg = <0x00 0x40>;
interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
misc_irq_mux: misc_irq_mux@80 {
compatible = "realtek,rtd1319-intc-misc";
reg = <0x00 0x80>;
interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
iso_irq_mux: iso_irq_mux@40 {
compatible = "realtek,rtd1319d-intc-iso";
reg = <0x00 0x40>;
interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
misc_irq_mux: misc_irq_mux@80 {
compatible = "realtek,rtd1319d-intc-misc";
reg = <0x00 0x80>;
interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
iso_irq_mux: iso_irq_mux@40 {
compatible = "realtek,rtd1325-intc-iso";
reg = <0x00 0x40>;
interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
misc_irq_mux: misc_irq_mux@80 {
compatible = "realtek,rtd1325-intc-misc";
reg = <0x00 0x80>;
interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
iso_irq_mux: iso_irq_mux@40 {
compatible = "realtek,rtd1619b-intc-iso";
reg = <0x00 0x40>;
interrupts-extended = <&gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
misc_irq_mux: misc_irq_mux@80 {
compatible = "realtek,rtd1619b-intc-misc";
reg = <0x00 0x80>;
interrupts-extended = <&gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
>
>Look at all other bindings covering multiple devices and their
>clocks/interrupts/interconnects/reg etc.
May I adopt the approach used in this YAML for my case?
https://www.kernel.org/doc/Documentation/devicetree/bindings/timer/allwinner%2Csun4i-a10-timer.yaml
Thank you for your feedback.
Regards,
James