Re: [PATCH 2/2] membarrier: riscv: Provide core serializing command

[Palmer Dabbelt]

On Wed, 06 Dec 2023 09:42:44 PST (-0800), parri.andrea@xxxxxxxxx wrote:
> > > The final version of this fix will likely depend on some machinery/code
> > > introduced by 3ccfebedd8cf54 ("powerpc, membarrier: Skip memory barrier
> > > in switch_mm()"); but, yes, nothing we can't safely adjust I think.
> >
> > Ya, I guess we'll have to look to know for sure but hopefully it's
> > manageable.
>
> Absolutely.  One approach would be to follow what PowerPC did: AFAIU, before
> 3ccfebedd8cf54 membarrier/powerpc used to hard code the required barrier in
> in finish_task_switch(), "masking" it as an smp_mb__after_unlock_lock(); riscv
> could use a similar approach (though with a different/new mask function).

IIRC we patterned our MMIOWB/after-spinlock barriers after PPC, so 
that's probably a good place to start here as well.

> Alternatively, we could maybe keep the barrier in switch_mm().
>
> But let me complete and send out v2 with the fix at stake...  this should give
> us a more concrete basis to discuss about these matters.
>
>   Andrea